Hitachi, Ltd.

Shiro Ohishi

Masatsugu Shinozaki

Yuuji Saeki

An information processing system is disclosed which includes an information processing apparatus having a plurality of slots on which a plurality of types of adapters can be mounted. Each type of the adapters has not its own address allocated by the system but will have, when mounted on any one of the slots, an address defined by the slot on which the adapter is actually mounted. In determining the system configuration, a processor accesses the addresses allocated to the slots sequentially and will receive adapter ID's from the adapters mounted on the slots.

Processing system and method for allocating address space among adapters

For transmitting binary data at a data transmission speed of F=1/[(N+1)T] bits/second, where N represents a value selected in accordance with a given transmission speed and T represents a predetermined constant period, a transmitter station sends out a bipolar signal on a transmission line for the period T (seconds) corresponding to one of the states of the binary data independent of the data transmission speed, while no data is sent out on the transmission speed, while no data is sent out on the transmission line for the period NT (seconds) as well as for a period corresponding to the other state of the binary data. In a receiving station, the binary states of the data are discriminatively determined from the bipolar signal received through the transmission line in accordance with the data transmission speed F, the data being converted to a unipolar signal such as NRZ signal.

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Hadano, Japan

Shiro Ohishi