Fujitsu Corporation

Shiro Kamoshida

Kenichi Kitamura

Kouji Kimura

Keisuke Nishida

Yuhei Takata

An arithmetic processing device, includes a memory; and a processor coupled to the memory and the processor configured to: execute arithmetic processing which executes a plurality of instructions issued out of order, execute control processing which commits the plurality of instructions for which execution has been completed in order, identify, for each instruction included in the plurality of instructions, a count value which indicates a number of cycles from when execution of the instruction has been completed, and identify, among a plurality of uncommitted instructions, the instruction with the count value which matches the number of cycles in which an error is detected in the arithmetic processing as a specific instruction to be retried.

Arithmetic processing device and semiconductor device with improved instruction retry

An adder-subtractor circuit includes an inverting circuit configured to invert a first operand on a bit-by-bit basis to output a first inverted operand, a circuit having a function to perform a predetermined arithmetic operation and configured to output a second operand, a carry generating circuit configured to generate carries from the first inverted operand and the second operand, and an XOR circuit configured to perform a bit-by-bit XOR on the carries, the first operand, and the second operand.

Adder-subtractor circuit and method of controlling adder-subtractor circuit

There is provision of a processing device including an instruction decoder and an arithmetic unit configured to process an immediate instruction for instructing a calculation of a product of an immediate value and a constant. In response to receiving the immediate instruction, the instruction decoder generates a first shift control information and a second shift control information based on the constant. The arithmetic unit generates a first shifted value by bit-shifting the immediate value received from the instruction decoder based on the first shift control information, and a second shifted value by bit-shifting the immediate value or a complement of the immediate value based on the second shift control information. By performing an addition of the first shifted value and the second shifted value, the arithmetic unit calculates the product.

Processing device, arithmetic unit, and control method of processing device

A processor includes: an error checking and correcting information generating unit; a storage unit configured to store data to which error checking and correcting information and error uncorrectable information are added when an error is detected and configured to store data to which error checking and correcting information is added when an error is not detected; and a processing unit configured to read out all data which the storage unit stores and configured to check an error of each piece of read-out data based on error checking/correcting information added to each piece of all the read-out data when an arithmetic unit detects an error, and configured to correct data in which an error is detected based on error checking and correcting information when a correctable error is detected.

Processor and control method of processor

A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.

Processor, control method of processor, and computer readable storage medium storing processing program for division operation

An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.

Error correction device, error correction method, and processor

An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log(n+1) bits of one portion of a redundant portion of error detecting/correcting-code-attached data by rounding up the numbers to the right of the decimal point of log(n+1) in response to the input of m bytes of an information portion included in error-detection-bit-attached data. The error-detection-bit-attached data includes a redundant portion of m bits of error detection bits allocated to the m bytes of the information portion, the byte having n bits. The circuit also includes a second exclusive OR operation circuit that generates m bits of another portion of the redundant portion of the error detecting/correcting-code-attached data in response to the input of the one portion and the error detection bits.

Error detecting/correcting code generating circuit and method of controlling the same

In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.

Arithmetic circuit, arithmetic processing device, and arithmetic processing method

When division X/Y of floating point numbers is performed, bit string data of a mantissa x including a fraction xf of X or a mantissa y including a fraction yf of Y is shifted in accordance with magnitude relation between them to perform a fraction computation. Thereby, a fraction division result in which the position of the most significant bit is fixed at a prescribed digit is generated. When a square root operation &#x221a;Y is performed, a fraction square root operation result in which the position of the most significant bit is fixed at a prescribed digit is generated by an exception handling if all of the three conditions that all the bits in the fraction of Y are one, a difference between the exponent ye of Y and a bias value b is an odd number, and a rounding mode is a positive infinity direction are satisfied.

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Kawasaki, Japan

Shiro Kamoshida