Mitsubishi Electric Corporation

Shiro Hino

Naruhisa Miura

Koji Sadamatsu

Masayuki Imaizumi

Hideyuki Hatta

Akihiko Furukawa

Yuichi Nagahisa

Kohei Ebihara

Yasuhiro Kagawa

Kotaro Kawahara

Hiroshi Watanabe

Kenichi Ohtsuka

Tomokatsu Watanabe

Shuhei Nakata

Takaaki Tominaga

Yutaka Fukui

Katsutoshi Sugawara

Shoyu Watanabe

Yukiyasu Nakao

Toshiaki Iwamatsu

Yoichiro Tarui

Rina Tanaka

Kazuya Konishi

Yuji Ebiike

Kohei Adachi

Yasushi Takaki

Yusuke Yamashiro

Akihiro Koyama

Yuji Abe

Masayoshi Tarutani

Naoki Yutani

Eisuke Suekawa

Sunao Aya

Kensuke Taguchi

Junichi Nakashima

Masayuki Furuhashi

Toshikazu Tanioka

Hidenori Koketsu

Shingo Tomohisa

Kosuke Miyazaki

Akemi Nagae

To mitigate adverse effects on a surface electrode of a semiconductor device. The semiconductor device includes: a first well region formed in a surface layer of an upper surface of a drift layer; a gate electrode; a second well region surrounding the first well region as seen in plan view; and a gate portion covering an interlayer insulation film and the gate electrode exposed from the interlayer insulation film. An outside edge portion of the gate electrode is farther from the first well region than an outside edge portion of the gate portion and closer to the first well region than an outside edge portion of the second well region.

Semiconductor device and power conversion device

The present disclosure relates to a silicon carbide semiconductor device, and includes a p-type second well region provided as an upper layer portion of a semiconductor layer; an n-type second impurity region provided as an upper layer portion of the second well region; a p-type second well contact region provided as an upper layer portion of the second well region; a field insulating film provided on the second well region; a second contact passed through the field insulating film electrically connected to a first main electrode; a boundary gate insulating film provided on a boundary between the element region and the non-element region; a boundary gate electrode provided on the boundary gate insulating film; and a second main electrode. The second well contact region extends from below the second contact toward the element region, and the second impurity region extends from below the second contact toward the non-element region.

Silicon carbide semiconductor device

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

Power converter

The fabrication method for a silicon carbide semiconductor device according to this disclosure includes a step of forming a dielectric film over part of a silicon carbide layer, a step of forming an ohmic electrode adjoining the dielectric film on the silicon carbide layer, a step of removing an oxidized layer on the ohmic electrode, a step of forming a mask with its opening on the side opposite to the side where the ohmic electrode is adjoining the dielectric film on the ohmic electrode having the oxidized layer removed and on the dielectric film, and a step of wet etching of a film to be etched with hydrofluoric acid with the mask formed. With the fabrication method for a silicon carbide semiconductor device described in this disclosure, it is possible to fabricate a silicon carbide semiconductor device with reduced failure.

Method for fabricating silicon carbide semiconductor device and power conversion device using the silicon carbide semiconductor device

An object of the present invention is to suppress the passage of bipolar current in a silicon carbide semiconductor device by reducing a voltage applied to a terminal well region during reflux operations. An SiC-MOSFET includes a plurality of first well regions, a second well region, a third well region in a surface layer of a drift layer, the first, second, and third well regions being of a second conductivity type. The third well region is provided on the side of the second well region opposite to the first well regions. A unit cell that includes the first well regions includes a unipolar diode. The SiC-MOSFET includes a source electrode connected to the unipolar diode and the ohmic electrode and not having ohmic connection with the second well region and the third well region.

Silicon carbide semiconductor device and power converter

A technique for maintaining maximum unipolar current density while improving I2t tolerance is provided. In a semiconductor device, a first impurity layer and a Schottky interface are formed to sandwich a well layer therebetween. A first impurity layer is formed from an outermost layer of the well layer located closer to the Schottky interface than a source layer to below the source layer. The lower face of the first impurity layer is located below the Schottky interface.

Semiconductor device

The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.

In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.

In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.

Silicon carbide semiconductor device having a conductive layer formed above a bottom surface of a well region so as not to be in ohmic connection with the well region and power converter including the same

In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.

In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.

A drift layer has a first conductivity type. A well region has a second conductivity type. A well contact region has a resistivity lower than that of the well region. A source contact region is provided on the well region, separated from the drift layer by the well region, and has the first conductivity type. A source resistance region is provided on the well region, separated from the drift layer by the well region, is adjacent to the source contact region, has the first conductivity type, and has a sheet resistance higher than that of the source contact region. A source electrode contacts the source contact region, the well contact region, and the source resistance region, and is continuous with the channel at least through the source resistance region.

A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.

A gate connection layer () includes a portion placed on an outer trench (TO) with a gate insulating film () being interposed. A first main electrode () includes a main contact (CS) electrically connected to a well region () and a first impurity region () within an active region (), and an outer contact (CO) being spaced away from the active region () and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region () is provided in a drift layer (). A trench-bottom high-concentration region () has an impurity concentration higher than that of the trench-bottom field relaxing region (), is provided on the trench-bottom field relaxing region (), and extends from a position where it faces the gate connection layer () with the gate insulating film () being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode ().

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Tokyo, Japan

Shiro Hino