Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Shiro Dosho

Shiro Sakiyama

Takashi Morie

Yusuke Tokunaga

Naoshi Yanagisawa

Kazuo Matsukawa

Masao Takayama

Yosuke Mitani

Akinori Matsumoto

Masaomi Toyama

Akira Matsuzawa

Hidehiko Kurimoto

Toru Iwata

Yoshito Date

Hiroyuki Nakahira

Yasuyuki Doi

Masayuki Ozasa

Takuji Miki

Kazuaki Sogawa

Tatsuo Okamoto

Akira Yamamoto

Takashi Hirata

Masakatsu Maruyama

Koji Obata

Makoto Mizuki

Hirokuni Fujiyama

Keijiro Umehara

Yutaka Terada

Keiichi Kusumoto

Kouji Okamoto

Noriaki Takeda

Seiji Watanabe

Hiroki Mouri

Tetsuro Omori

Yuji Yamada

Makoto Hattori

Tatsuro Juri

Masaya Sumita

Shinichi Yamamoto

Masahiro Fukui

Takefumi Yoshikawa

Hitoshi Kobayashi

Norihide Kinugasa

Yukihiro Sasagawa

Toshiyuki Shono

Masaru Fukuda

Koji Mochizuki

Takahiro Bokui

Tetsuro Ohmori

Kazuhiko Nishikawa

Masatoshi Matsushita

Hiroshi Koshida

Kazuhiko Nagaoka

Hirofumi Nakagawa

George Hayashi

Tetsurou Oomori

Kurumi Nakayama

Seizo Inagaki

Ryoichi Suzuki

Kaori Nishikawa

Hideki Yoshii

A delta sigma modulator includes a filter circuit including an integrator having an operational amplifier; a first addition circuit provided between an output section of the filter circuit and an input section of a quantizer, and including a first resistive element; and a second addition circuit including at least one of a first feedforward circuit including a second resistive element or a first feedback circuit configured to feed back, as an analog signal, a digital output signal having been quantized by the quantizer, to an input section of the quantizer, wherein at least one of the first addition circuit or the first feedback circuit includes a phase compensator.

Delta sigma modulator, as well as receiver device and wireless communication device provided with same

A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N&#x2212;1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value.

Time-to-digital converter and an A/D converter including the same

An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.

Oversampling time-to-digital converter

A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors.

Time difference adjustment circuit and time-to-digital converter including the same

Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

Resonator and oversampling A/D converter

A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Time-to-digital conversion circuit and time-to-digital converter including the same

An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

Oversampling A/D converter

A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Time integrator and &#x394;&#x3a3; time-to-digital converter

A delta-sigma modulator includes: an integrator having an operational amplifier; a quantizer quantizing an output of the integrator; a first D-A converter converting an output of the quantizer to a current signal to provide negative feedback to the operational amplifier; a feedforward path feeding forward an input of the integrator to the quantizer; and a second D-A converter converting the output of the quantizer to a current signal to provide negative feedback to the quantizer. The integrator includes a resistive element having a first end connected to the input of the integrator and a second end connected to an inverting input of the operational amplifier, n capacitive circuits connected in series between the inverting input and an output of the operational amplifier, and (n&#x2212;1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.

Delta-sigma modulator, integrator, and wireless communication device

An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

Time-to-digital converter

An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner.

A/D converter

In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from &#x2212;(2&#x2212;1) to +(2&#x2212;1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Time-to-digital conversion stage and time-to-digital converter including the same

Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.

Resonator, delta-sigma modulator, and wireless communication device

A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n&#x2212;1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n&#x2212;1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n&#x2212;1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n&#x2212;1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.

Integrator and oversampling A/D converter having the same

An oversampling A/D converter with a few operational amplifiers is configured using a complex second-order integrator including first and second second-order integrators and first and second coupling circuits configured to couple these integrators together. Each of the second-order integrators includes an operational amplifier, four resistance elements, and three capacitance elements. The first coupling circuit cross-couples one of two serially-connected capacitance elements inserted between the inverted input terminal and output terminal of the operational amplifier in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements. The second coupling circuit cross-couples the other capacitance element in the first second-order integrator to the counterpart in the second second-order integrator using two resistance elements.

Complex second-order integrator and oversampling A/D converter having the same

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Osaka, Japan

Shiro Dosho