Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer System, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Vsli Engineering Corp.

Vlsi Engineering Corporation

Shiro Baba

Yasushi Akao

Kenichi Kuroda

Kiyoshi Matsubara

Kazuyoshi Shiba

Masanao Sato

Takashi Ito

Masaaki Terasawa

Naoki Yashiki

Hirofumi Mukai

Keiichi Kurakazu

Kouki Noguchi

Shigeki Masumura

Takanaga Yamazaki

Takashi Tsukamoto

Mitsuru Watabe

Shumpei Kawasaki

Toshimasa Kihara

Yugo Kashiwagi

Masahiro Kainaga

Kaoru Fukada

Yoichi Asano

Katsuhiko Ishida

Eiji Sakakibara

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Toru Baji

Atsushi Kiuchi

Koki Noguchi

Hiroshi Ohsuga

Hironobu Hasegawa

Yoshimune Hagiwara

Terumi Sawase

Hideo Nakamura

Satoshi Masuda

Naoki Mitsuishi

Hiroyuki Kida

Yuji Hatano

Tsutomu Hayashi

Yoshikazu Aoto

Hisao Sasaki

Shinji Kawashima

Yoshiaki Naruse

Hiromi Nagayama

Yukihide Hayakawa

Takeshi Miyazaki

Kunihiko Nakada

Toshio Tanaka

Susumu Matsui

Toshio Okochi

Kenji Kawakita

Jiro Kashio

Matsuaki Terada

Yuji Sato

Fumio Tsuchiya

Yoshiyuki Miwa

Susumu Kaneko

Makoto Takano

Yasuhiko Hoshi

Masaharu Ando

A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Data processing device having a central processing unit and digital signal processing unit

Method for manufacturing a printed board on which a semiconductor device having two modes is mounted

Microcomputer including a flash memory that is two-way programmable

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions

Growing community of inventors

Kokubunji, Japan

Shiro Baba