International Business Machines Corporation

Shiri Moran

Bodo Hoppe

Eli Arbel

Erez Barak

Ziv Nevo

Gil Eliezer Shurek

Vitali Sokhin

Tom Kolan

Udo Krautz

Shlomit Koyfman

Chung-Lung K Shum

Pradip Bose

Patrick James Meaney

K Paul Muller

Prabhakar Nandavar Kudva

Dean G Bair

Alexander Ivrii

Gabor Bobok

Benjamin Neil Trombley

Hana Chockler

Douglas G Balazich

Osher Yifrach

Tatyana Veksler

Sharon Keidar Barner

Sitvanit Ruah

Erica Stuecheli

Arie Matsliah

Karl Evan Smock Anderson

Arvind Haran

Ido Rozenberg

Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Error protection analysis of an integrated circuit

A system, program product, and method for validating a system under test (SUT). The method includes generating one or more application programming interface (API) requests. The method also includes selecting one or more random biases for one or more properties of the one or more API requests. The method further includes generating a random sample of one or more values from an input domain space, wherein the one or more values are associated with one or more respective fields of the API being requested.

Test space sampling for model-based biased random system test through rest API

Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.

Model-based biased random system test through rest API

Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

Testing netlists based on singular independent signals

A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Assuring chip reliability with automatic generation of drivers and assertions

A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Template matching for resilience and security characteristics of sub-component chip designs

A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Method and apparatus for testing

Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.

Incremental formal verification

A computerized system comprising: a processor; a first interface configured to obtain a constraint; a second interface configured to obtain a first model, wherein the first model is configured to be utilized in model checking, and the first model, when constrained by the constraint, comprises at least one finite path; and a finite path removal module implemented in the processor and configured to generate a second model equivalent to the first model obtained by said second interface, wherein the second model excludes a portion of the at least one finite path, and the second model is configured to be utilized in model checking.

Model generation based on a constraint and an initial model

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Kiryat Tivon, Israel

Shiri Moran