Qualcomm Incorporated

Lsi Logic Corporation

Future Wei Technologies, Inc.

Huawei Technologies Co., Limited

Nantero, Inc.

Lsi Corporation

Philips Healthcare Informatics, Inc.

Shiqun Gu

Matthew Michael Nowak

Jonghae Kim

Dong Wook Kim

Changhan Hobie Yun

David Francis Berdy

Brian Matthew Henderson

Chengjie Zuo

Hong Bok We

Vidhya Ramachandran

Jae Sik Lee

Kenneth Kaskoun

Mario Francisco Velez

Niranjan Sunil Mudakatte

Hong Lin

Seung Hyuk Kang

Thomas R Toms

Ratibor Radojcic

Peter McGrath

Xia Li

Wai Lo

Rongtian Zhang

Je-Hsiung Lan

Urmi Ray

Lew G Chua-Eoan

Steve Fanelli

Hongying Zhang

Xiaochun Zhu

Richard Hammond

Yang Du

Feng Wang

Bart Swinnen

Ryan Tadashi Fujimoto

Jinghua Zhu

Thomas Rueckes

Jung Pill Kim

Daeik Daniel Kim

Michael Andrew Stuber

Wilbur G Catabay

Sinan Goktepeli

Young Kyu Song

Jeffrey Xu

Taehyun Kim

Zhihai Wang

Wei-Jen Hsia

Seyfollah Seyfollahi Bazarjani

Ryan David Lane

Hong Liu

Richard Carter

Reza Jalilizeinali

Chiew-Guan Tan

Eugene Dantsker

Jun Xia

Arvind Chandrasekaran

Hongquan Sun

Shree Krishna Pandey

James R B Elmer

Wangsheng Xie

Plamen Vassilev Kolev

Derryl J Allman

Yu Cao

Liming Zhao

Dexter Tamio Chun

Francesco Carobolante

Kangho Lee

Jungwon Suh

Choh Fei Yeap

Peter Austin Burke

Eugene Robert Worley

Guofang Jiao

Derryl D J Allman

Russel A Martin

John Jianhong Zhu

Byung-Sung Kwak

Hong Tao Liu

Anand Srinivasan

Gengming Tao

Kyu-Pyung Hwang

Sey-Shing Sun

Chin-Kwan Kim

Yu Lu

Ranadeep Dutta

Hemanshu D Bhatt

Daniel Daeik Kim

Verne C Hornback

David Boettcher Baek

William Xia

Jing Xie

Michael Laisne

Jun Chen

Glenn D Raskin

Jihong Choi

Zhongping Bao

Masaichi Eda

Yong Ju Lee

Richard J Carter

Christine Sung-An Hau-Riege

Husnu Ahmet Masaracioglu

Wenyue Lydia Zhang

Daniel Wayne Perry

A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

Multi-tier IC package including processor and high bandwidth memory

The disclosure relates to technology for determining stress on integrated circuits. These include using ring oscillators formed on the integrated circuit, where one ring oscillator has its frequency dependent on the current flowing through its stages being limited by its NMOS devices and another ring oscillator has its frequency dependent on the current flowing through its stages being limited by its PMOS devices. This allows the stress on the integrated circuit to be determined in different directions along the integrated circuit. A temperature sensor can be used to compensate for temperature dependence on the frequencies of the ring oscillators.

Complementary ring oscillators to monitor in-situ stress within integrated circuits

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

Merged power pad for improving integrated circuit power delivery

A multi-chip module includes a first Integrated Circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, the first interleaved interconnections including a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

IC die to IC die interconnect using error correcting code and data path interleaving

Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

Wrapped signal shielding in a wafer fanout package

A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

Bottom package with metal post interconnections

An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

Hybrid passive-on-glass (POG) acoustic filter

An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Integrated circuits (ICs) on a glass substrate

A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

Semiconductor package having reduced internal power pad pitch

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

Heterogenous 3D chip stack for a mobile processor

In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

Glass substrate including passive-on-glass device and semiconductor die

An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

Integrated device comprising a capacitor and inductor structure comprising a shared interconnect for a capacitor and an inductor

A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the secod encapsulation layer at least partially encapsulates the second plurality of filters.

Package comprising switches and filters

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San Diego, CA, United States of America

Shiqun Gu