National Science Council

National Science Council of Republic of China

National Cheng-Kung University

Shiou-Ying Cheng

Wen-Chau Liu

Huey-Ing Chen

Wen-Chan Liu

Wei-Chou Wang

A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Heterojunction bipolar transistor with zero conduction band discontinuity

An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a &dgr;-doped sheet. Moreover, the use of a setback layer with a thickness of 50 &angst; added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.

Negative-differential-resistance heterojunction bipolar transistor with topee-shaped current-voltage characteristics

In this invention, a new, simple and small-size hydrogen-sensitive palladium (Pd) membrane/semiconductor Schottky diode sensor has been developed and fabricated. First, a high quality undoped GaAs buffer layer and an n-type GaAs epitaxial layer with the carrier concentration of 2.times.10.sup.17 cm.sup.31 3 is grown by molecular beam epitaxy (MBE) on a semi-insulated GaAs substrate. Then a thin Pd membrane is evaporated on the surface of the n-type GaAs epitaxial layer by the vacuum evaporation technique. It is well-known that palladium metal has excellent selectivity and sensitivity on hydrogen gas. When hydrogen gas diffuses to the Pd membrane surface, the hydrogen molecules will dissociate into hydrogen atoms. Some of the hydrogen atoms diffuse through the thin metal layer and form the palladium hydride near the metal-semiconductor interface. The hydride may effectively lower the work function of Pd metal. The lowering of work function results in the reduction of Schottky barrier height at the Pd metal-GaAs semiconductor interface and the modification in the measured current-voltage characteristics of the studied device. Experimental results reveal that, during the hydride formation process, the forward- and reverse-biased currents are increased by the increase of hydrogen concentration. It also demonstrates that the Schottky barrier height is indeed decreased with increasing the hydrogen concentration. Therefore, the studied device can be used in fabricating a high-performance hydrogen-sensitive sensor.

Hydrogen-sensitive palladium (PD) membrane/semiconductor schottky diode

The invention is to develop a high-speed low power consumption resonant tunneling element--a superlatticed negative-differential-resistance (NDR) functional transistor. The proposed element exhibits amplification and obvious NDR phenomena simultaneously. In this element, the emitter region includes 5-period GaInAs/AlInAs super lattice resonant tunneling and emitter layers. Since the emitter--base interface is of homojunction, the collector--emitter offset voltage (V.sub.CE, offset) may be lowered down significantly. In addition, the produced infinitesimal potential (.DELTA.Ev) at GaInAs/AlInAs interface due to heterojunction in discrete valence bands may be applied as barriers to prohibit holes flow from base towards emitter. By doing so, the base current is remarkably depressed so as to elevate efficiency of emitter injection as well as current gain.

Superlatticed negative-differential-resistance functional transistor

Structure of a wide voltage operation regime double heterojunction bipolar transistor, specifically a modified InGaP/GaAs double heterojunction bipolar transistor featuring a very broad collector-emitter voltage operation range, an invention of high speed, low power consumption and high breakdown voltage rated microwave power transistor. Unique in the incorporation of In.sub.0.49 Ga.sub.0.51 P collector layer, GaAs delta-doping sheet and undoped GaAs spacer in the collector zone. The introduction of a spacer with a delta doping sheet into the effective base-collector heterojunction serves to eliminate potential spike from appearing at base-collector interfacing any more, thus effectively precludes electron blocking effect. In the emitter zone the inventive design comprises a five-period In.sub.0.49 Ga.sub.0.51 P/GaAs superlatticed confinement layer to GaAs emitter homojunction, with superlatticed confinement layer functioning as a containment layer for minority (hole), while the base-emitter homojunction homojunction serves to control the majority (electron) being emitted from the emitter into the base. That achieves an enhanced emitter injection efficiency and lowered offset voltage at the same time, as such, the invention transistor is very fit for application in digital as well as analogue circuits preconditioned by high speed, low power consumption, and high breakdown voltage performances.

Wide voltage operation regime double heterojunction bipolar transistor

A new high-speed resonant tunneling device, namely, a long-period superlattice resonant tunneling transistor, is developed according to the invention. The structure of the proposed 20-period superlattice resonant tunneling transistor consists of an InP substrate, a buffer layer formed by GaInAs material on the substrate, a collector layer formed by GaInAs material on the buffer layer, a base layer formed by GaInAs material on the collector layer, an emitter layer formed by GaInAs material on the base, a 20-period superlattice resonant tunneling layer formed by AlInAs and GaInAs materials on the emitter layer, and an ohmic contact layer formed by GaInAs material on the 20-period superlattice resonant tunneling layer. Furthermore, the emitter region includes a 20-period AlInAs/GaInAs superlattice and an emitter layer. Due to the presence of an emitter-base homojunction, collector-emitter offset voltage (V.sub.CE,offset) can be reduced significantly. In addition, the valence band discontinuity (.DELTA.Ev) at the AlInAs/InGaAs heterojunction may be used as a barrier for holes injected from the base toward the emitter region. Therefore, the emitter injection efficiency and current gain can be increased. From the theoretical analysis and computer simulation, two subbands are observed in the superlattice region. Under the proper applied bias, the studied device will create n-type negative differential resistance (NDR). Consequently, the proposed device shows good promise for use in amplification, parity generator, and multiple-value logic circuit applications.

Growing community of inventors

Tainan, Taiwan

Shiou-Ying Cheng