Fujitsu Corporation

Fujitsu Semiconductor Limited

Kyushu Fujitsu Electronics Limited

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Fijitsu Limited

Shinya Udo

Masatoshi Kokubun

Masao Kumagai

Osamu Kudo

Chikara Tsuchiya

Seiji Yamagata

Fumitaka Asami

Toshihiko Kasai

Yoshihiro Kizaki

Hideto Fukuda

Katsuyosi Yamamoto

Takeo Shigihara

Hidekazu Nishizawa

Jun Funakoshi

Satoru Masaki

Fusao Seki

Motoki Shimozono

Akinori Yamamoto

Kazuo Ohno

Masao Imai

A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.

D/A converter

A plurality of DC-DC converters are cascade-connected via a plurality of control signal lines which are used in common for start sequence control and stop sequence control. Each of the plurality of DC-DC converters is constituted including a sequence control circuit which commences a start operation along with activation of a control signal line on a previous stage side and activates a control signal line on a subsequent stage side along with completion of the start operation, and commences a stop operation along with deactivation of the control signal line on the subsequent stage side and deactivates the control signal line on the previous stage side along with completion of the stop operation.

Power supply circuit, power supply control circuit and power supply control method

A driver IC for a display that includes a first D/A converter with a 1selection circuit that receives 1image signals and supplies a selected positive divisional voltage to a 1operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2D/A converter with a 2selection circuit that receives 2image signals and supplies a selected negative divisional voltage to a 2operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1and 2switches connecting the 1and 2D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1and 2image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1and 2switches in a complementary manner.

Driver IC for display and display including same

An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period Hwhich is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC, thereby changing the output voltage VO() only by the offset voltage VO() by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data Dto Dconducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Operational amplifier, line driver, and liquid crystal display device

A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Semiconductor device and liquid crystal panel driver device

Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Semiconductor integrated circuit for driving liquid crystal panel

A differential amplifying circuitincludes a current mirror circuit having first and second current ends to which drains of MOS transistors Mand Mare respectively connected, and a pair of differential MOS transistors Mand Mhaving gates between which a switch SWis connected. A reference potential Vref is applied to the gate of the MOS transistors M. A switch SWis connected between the output VO of an output buffer circuitand the gate of a MOS transistor M, and a switch SWis connected between the output VO and the gate of the MOS transistor M. During the offset-cancel preparation period, the switches SWand SWare on and the switch SWis off. Next, the switches SWto SWare turned over, consequently outputting offset-canceled potential VO.

Offset cancel circuit of voltage follower equipped with operational amplifier

A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

Method for driving display and drive circuit for display

The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiodea source follower amplifierfor converting an electric charge of the photodiodeinto a voltage and amplifying it to output image data, and a horizontal selection transistorfor outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuithas a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.

X-Y address type solid-state image pickup device with an image averaging circuit disposed in the noise cancel circuit

A display device includes a plurality of data drivers which are cascade-connected, and prevents variation of the duty ratio of a signal caused by accumulation of errors. In each of the plurality of data drivers: a first input circuit receives a first signal supplied from outside; a second input circuit receives a second signal supplied from outside, in response to the first signal received by the first input circuit; a signal processing circuit performs signal processing based on the second signal received by the second input circuit; a first output circuit inverts the first signal received by the first input circuit, and outputs the inverted first signal; and a second output circuit delays the second signal received by the second input circuit, by a predetermined amount, and outputs the delayed second signal.

Semiconductor device, display device, and signal transmission system

An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.

Integrated circuit free from accumulation of duty ratio errors

A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data signal from being transferred to a data output circuit when a data signal captured by a data capturing circuit is to be latched by a latch circuit. If however, the data signal captured is necessary for a later stage of the semiconductor device, then an internal data transfer blocking circuit blocks the data signal from being latched in the latch circuit, while the clock transfer blocking circuit and the external data transfer blocking circuit cause the captured clock signal and data signal to be output to the data output circuit.

Growing community of inventors

Kawasaki, Japan

Shinya Udo