Renesas Electronics Corporation

Nec Corporation

Shinya Tashiro

Kazutaka Taniguchi

Takayuki Ibaraki

A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.

Semiconductor device having CMOS transfer circuit and clamp element

A semiconductor device includes an internal power-supply circuit which produces an internal potential, an external terminal which outputs the internal potential and inputs and outputs a signal with an outside, and a test mode signal terminal which transfers a test mode signal. The semiconductor device further includes a first CMOS transfer circuit and a second CMOS transfer circuit which are provided between the internal power-supply circuit and the external terminal, and which are controlled by the test mode signal, a clamp element which is connected between the first and second CMOS transfer circuits and suppresses a potential variation, and a delay element provided between the clamp element and the first CMOS transfer circuit.

It is desired to reduce the current consumption of an autonomous impedance adjustment circuit. The semiconductor integrated circuit according to the present invention stops the change in the drive capability of a driver correspondingly to the output (count data) of a comparator which is sequentially outputted for changing the drive capability of a replica driver and an output driver.

Semiconductor integrated circuit, semiconductor storage device and impedance adjustment method

A semiconductor synchronous dynamic random access memory device has an input/output masking function in a block write mode, plural bit line pairs are concurrently connected to a pair of data lines charged to a power voltage level by a precharge circuit in the input/output masking function so as to prevent memory cells from current flowing out from differential amplifiers, and the precharge circuit has not only p-channel type charging transistors but also n-channel enhancement type charging transistors; even if the bit line pairs are connected to the pair of data lines, the n-channel enhancement type charging transistors supplement the current through the data line pair to the bit line pairs, and prevent potential differences on the bit line pairs from undesirable destruction.

Growing community of inventors

Kanagawa, Japan

Shinya Tashiro