Mitsubishi Electric Corporation

Shinya Soneda

Koichi Nishi

Kenji Harada

Tetsuya Nitta

Ryu Kamibaba

Akihiko Furukawa

Kazuya Konishi

Hiroyuki Nakamura

Kakeru Otsuka

Masanori Tsukuda

Tetsuo Takahashi

Masayoshi Tarutani

Takahiro Nakatani

Munenori Ikeda

Koji Tanaka

Atsushi Narazaki

Hidenori Fujii

Yosuke Nakata

Tomohiro Tamaki

Taketoshi Shikano

Mitsuru Kaneda

Shoichi Kuga

Norikazu Sakai

In plan view of an RC-IGBT, a boundary region has an occupancy rate of an n-type source layer per unit area, the occupancy rate being smaller than an occupancy rate of the n-type source layer per unit area in an IGBT region, and the boundary region has an occupancy rate of a p-type contact layer per unit area, the occupancy rate being smaller than an occupancy rate of the p-type contact layer per unit area in an IGBT region.

Semiconductor device

When a positive gate voltage is applied to a first one of a first gate electrode and a second gate electrode, and current flows from a collector electrode to an emitter electrode, a semiconductor device applies a positive gate voltage to a second one of the first gate electrode and the second gate electrode. When a positive gate voltage is applied to the first one and current flows from the emitter electrode to the collector electrode, the semiconductor device applies voltage equal to or less than reference voltage to the second one.

Semiconductor device and method for controlling semiconductor device

Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.

Semiconductor device and method for controlling the same

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Semiconductor device and method of manufacturing semiconductor device

According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

There is provided a technique capable of reducing turn-on power losses. A semiconductor device includes: a semiconductor substrate including a drift layer; and a base layer, a contact layer, and a source layer which are provided in the semiconductor substrate. A gate portion is provided in a first trench, with a first gate insulation film therebetween. The first trench is in contact with the contact layer, the source layer, the base layer, and the drift layer. The gate portion is provided with a recessed portion with a bottom farther away from the base layer than a side thereof. A first insulation portion is provided in the recessed portion of the gate portion in the first trench.

A first principal electrode and a first control electrode pad are formed on a first principal surface of the semiconductor chip. A second principal electrode and a second control electrode pad are formed on a second principal surface of the semiconductor chip. The second principal electrode and the second control electrode pad are respectively bonded to first and second metal patterns of an insulating substrate. Bonding sections of first and second wires overlap a bonding section of the second principal electrode or the second control electrode pad in plan view. Thickness of the first and second metal patterns is 0.2 mm or less.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface.

RC-IGBT with lifetime control layer

A semiconductor device includes a first contact layer connected to a lower portion of a first trench contact portion and a second contact layer connected to a lower portion of a second trench contact portion. The distance between a first side portion of a first trench and the first trench contact portion is larger than that between a second side portion of the first trench and the second trench contact portion in a plan view, and the first contact layer is separated from the first side portion and the second contact layer is connected to the second side portion in a cross section. With this structure, it is possible to provide a technique for achieving an appropriate channel region.

All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Semiconductor device and method for manufacturing the same

The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.

An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

Method of manufacturing semiconductor device

The semiconductor substrate has a first principal surface and a second principal surface. The base contact layer is arranged between the base layer and the first principal surface, and forms a part of the first principal surface. The anode contact region is arranged between the anode layer and the first principal surface, forms a part of the first principal surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer. The anode contact region includes a first anode contact layer having a lower net concentration and a higher first conductivity type impurity concentration than the base contact layer.

Reverse conducting semiconductor device and method for manufacturing reverse conducting semiconductor device

Provided is a semiconductor device in which a first anode layer and a first contact layer are provided on a first main surface side in a diode region, and in which a second anode layer and a second contact layer are provided on the first main surface side in a boundary region. A concentration of impurities of a second conductive type of the second anode layer is lower than a concentration of impurities of the second conductive type of the first anode layer, or an occupied area ratio of the second contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the boundary region is smaller than an occupied area ratio of the first contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the diode region.

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Tokyo, Japan

Shinya Soneda