Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Shinya Soeda

Atsushi Hachisuka

Takayuki Saito

Nobuyuki Yoshioka

Koji Taniguchi

Yuki Miyamoto

Koichiro Narimatsu

Ayumi Minamide

Shigenori Yamashita

Hiroyasu Nohsoh

Tomohiro Yamashita

Yoshinori Okumura

Hiroki Shinkawata

Hidenori Sato

Masato Fujinaga

Tatsuo Kasaoka

A semiconductor device has a semiconductor substrate and a resistor group and/or a signal interconnection layer in a region of the semiconductor substrate. A shielding layer is located above and/or below the region where the resistor group and/or the signal interconnection layer are located.

Semiconductor device and method of fabricating the same

Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns and having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions are extracted followed by as many smaller free regions as possible. The dummy patterns are laid out in the extracted free regions.

Semiconductor device, semiconductor device pattern designing method, and semiconductor device pattern designing apparatus

A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.

Semiconductor device comprising a dual gate CMOS

A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N diffusion layer according to a silicide process. Thereafter, a second silicide protection film is deposited, a second resist pattern having an opening at a prescribed position is formed, portions of the first and second silicide protection films exposed from the opening of the second resist pattern are removed to form a second opening in the first and second silicide protection films, a P diffusion layer is formed in a portion of the silicon substrate exposed from the second opening, the second resist pattern is removed, and a metallic film is deposited to form a second silicide layer on the P diffusion layer according to the silicide process. Therefore, silicide layers having characteristics optimum to the diffusion layers can be formed, and the number of mask matching operations can be reduced.

Method of manufacturing semiconductor device

The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.

Semiconductor device and method of manufacturing the same

A technique of correcting a mask pattern without alleviating the design rule or measuring all contact hole diameters. Undulations are inspected in a region for forming contact holes (step S ). On the basis of the surface shape (undulations) determined at step S , the contact hole diameter is predicted in the case of use of the mask hole diameter fabricated at step S (step S ). On the basis of the result of prediction, the mask pattern M is corrected to mask patter M&prime; according to the mask hole diameter (step S ).

Method of making a mask pattern

A semiconductor substrate is arranged to have a DRAM area in which to form at a high density gate electrodes of transistors serving as DRAM components, and a peripheral circuit area in which to form at a relatively low density gate electrodes of transistors as peripheral circuit components. A resist film is formed in corresponding relation to the gate electrodes of the DRAM. After an insulating film is etched, a resist film is formed in corresponding relation to the gate electrodes of the peripheral circuits. A conductive layer is then etched while the resist film and insulating film left in the DRAM area are being used as masks, whereby the gate electrodes are formed in the DRAM area and peripheral circuit area.

Manufacturing method of a semiconductor device for desired circuit patterns

The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof

A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.

Method of manufacturing a DRAM and logic device

Registration accuracy measurement mark, method of repairing defect of

Registration accuracy measurement mark

In a memory cell formed of one transistor and one capacitor, the capacitor includes a stacked type capacitor region extending over the gate electrode and word line of the transfer gate transistor, and a trench type capacitor region extending into a groove part formed in the field isolation film for element separation. The trench type capacitor region is formed between a pair of word lines extending on the field isolation film. Each storage node of adjacent capacitors is isolated on the bottom surface of the groove.

Growing community of inventors

Tokyo, Japan

Shinya Soeda