Toshiba Memory Corporation

Winbond Electronics Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Windbond Electronics Corp.

Shinya Okuno

Shigeki Nagasaka

Toshiyuki Kouchi

Masaru Koyanagi

Masahiro Yoshihara

Mikihiko Ito

Masafumi Nakatani

Akira Umezawa

Kazushige Kawasaki

Satoshi Tsukiyama

Yasuhiro Hirashima

Mami Kakoi

A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.

Delay control circuit, semiconductor memory device, and delay control method

Provided is a delay control circuit that can prevent an N-value detection sequence performed by the delay control circuit from exceeding a specific period. The delay control circuit includes: a DLL control circuit that sets a delay amount; a delay line circuit that performs a delay operation; and an N-value detection circuit that receives an input clock signal and an output clock signal and is configured to perform a pre-N-value detection operation. The pre-N-value detection operation includes detecting the number of delayed clock cycles from the input clock signal to the output clock signal as the number of pre-delayed clock cycles before a delay operation is performed. In response to that the number of pre-delayed clock cycles is not greater than a specific value, the DLL control circuit changes the delay amount so that the delay line circuit performs the delay operation in a fast mode.

A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Semiconductor device

According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Memory device

A memory device and a refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area near the plurality of normal areas. The redundancy area includes a plurality of redundancy word lines. A plurality of boundary word lines are arranged near boundaries between the plurality of normal areas and the redundancy area. The controller refreshes the plurality of redundancy word lines in sequence, and refreshes the plurality of boundary word lines in sequence after refreshing the plurality of redundancy word lines in sequence.

Memory device for refreshing redundancy area word lines, and refresh method thereof

A DLL device and an operation method for the DLL device are provided. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays an input clock in response to a delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delayed clock. The phase detector compares the input clock with the feedback clock to generate a delay control signal. The delay controller generates the delay code at a first time point according to the delay control signal based on a control clock and delays a replica delay time length to provide the delay code to the delay line at a second time point. The delay line adjusts the input clock at the second time point. A cycle of the control clock is adjusted to be larger than the replica delay time length.

Delay-locked loop device and operation method therefor

A memory device and a row-hammer refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area adjacent to the plurality of normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged. The controller is configured to row-hammer refresh the plurality of normal areas without row-hammer refreshing the redundancy area.

Memory device and row-hammer refresh method thereof

A delay locked loop device (DLL) and an update method therefor are provided. The DLL device includes a DLL and an update circuit. The DLL is enabled according to an enable signal, thereby delaying an input clock to provide a delayed clock. The update circuit includes a flag generating circuit and an enable circuit. The flag generating circuit provides an update flag based on a default time interval. The enable circuit triggers the enable signal to a first logic level according to the update flag, and transitions the enable signal from the first logic level to a second logic level before the end of the default time interval. The default time interval is shorter than the refresh cycle of the memory.

Delay locked loop device and update method thereof

According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

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Yokohama, Japan

Shinya Okuno