Nec Corporation

Shinya Oda

Fumitoshi Mizutani

A controller includes a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an instruction input to the target device and a response to the instruction input, predicting a response of the target device to the instruction acquired, and outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and a master circuit connected to the target device with the bus, the master circuit transmitting the instruction to the target device through the bus, and performing initial setting of the target device based on the fault report from the pseudo device circuit.

Controller, bus circuit, control method, and recording medium

Each of memory bridges and I/O bridges, cross-linked to one another, is provided with an interface circuit section which performs data transmission and reception according to an PCI-Express interface. Each interface circuit section has a communication error processing section. When an error occurs in data received from the I/O bridge, the communication error processing section of the memory bridge cancels the received data and sends a communication error signal to the memory bridge. When receiving the communication error signal, the memory bridge stops receiving the data. Then, the communication error processing section of the memory bridge requests the I/O bridge to resend data.

Growing community of inventors

Tokyo, Japan

Shinya Oda