Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Shinya Nishimura

Narumasa Soejima

Yuichi Takeuchi

Hirokazu Fujiwara

Kensaku Yamamoto

A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

Semiconductor device and manufacturing method thereof

A semiconductor device is provided with: a first conductivity type contact region; a second conductivity type body region; a first conductivity type drift region of; a trench formed through the contact region and body region from a front surface of the semiconductor substrate, wherein a bottom of the trench is positioned in the drift region; an insulating film covering an inner surface of the trench; a gate electrode accommodated in the trench in a state covered with the insulating film; and a second conductivity type floating region formed at a position deeper than the bottom of the trench, and adjacent to the bottom of the trench. The floating region includes a first layer adjacent to the bottom of the trench and a second layer formed at a position deeper than the first layer, wherein a width of the first layer is broader than a width of the second layer.

Growing community of inventors

Nisshin, Japan

Shinya Nishimura