Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Shinya Naito

Takayuki Kakegawa

Tatsufumi Hamada

Takashi Izumida

Nobutoshi Aoki

Hikari Tajima

Takaya Yamanaka

Yoshiaki Fukuzumi

Hiroshi Kanno

Mitsutoshi Nakamura

Tomofumi Zushi

Osamu Fujii

According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.

Semiconductor device and control method

A semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; a semiconductor pillar extending through the electrode layers in a stacking direction and electrically connected to the conductive layer; and an insulating layer positioned between the semiconductor pillar and the electrode layers and extending along the semiconductor pillar. The semiconductor pillar has a channel portion extending through the electrode layers and a high impurity concentration portion positioned at a bottom end on a side of the conductive layer. The high impurity concentration portion includes an impurity of a higher concentration than an impurity concentration in the channel portion. The insulating layer has an end portion extending toward a center of the bottom end of the semiconductor pillar, and a boundary of the channel portion and the high impurity concentration portion is positioned above the end portion of the insulating layer.

Semiconductor memory device

According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.

Three dimensional semiconductor memory device in which a channel layer has a stacked structure including an outer semiconductor layer and a doped inner semiconductor layer

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

Method for manufacturing a semiconductor device including a vertical channel between stacked electrode layers and an insulating layer

According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. The second conductive layer is provided between the base semiconductor layer and the first conductive layer. The semiconductor body extends through the first conductive layer in the first direction. The memory layer is provided between the semiconductor body and the first conductive layer. The first semiconductor region is provided between the memory layer and the base semiconductor layer and between the semiconductor body and the base semiconductor layer, and is of a first conductivity type. The second semiconductor region is provided between the first semiconductor region and the memory layer, and is of a second conductivity type.

Semiconductor device having vertical channel between stacked electrode layers and insulating layers

According to one embodiment, a substrate includes a first portion and a second portion. The first portion has a columnar configuration. The second portion has an upper surface continuous with a side surface of the first portion via a corner. A plurality of electrode layers include a lowermost electrode layer opposing the side surface of the first portion above the second portion. An insulating film is provided between the side surface of the first portion and a side surface of the lowermost electrode layer, and between the upper surface of the second portion and a lower surface of the lowermost electrode layer. An angle formed between the upper surface of the second portion and the corner of the substrate on the insulating film side is greater than 90&#xb0;.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate, a semiconductor pillar and an electrode member provided inside the stacked body, a charge storage film, and a control circuit. The stacked body includes insulating films and electrode films stacked alternately. The semiconductor pillar and the electrode member extend in a stacking direction and lower ends thereof are connected to the semiconductor substrate. The charge storage film is provided between the semiconductor pillar and one of the electrode films. The control circuit sets an upper end of the semiconductor pillar to a floating state, applies a first potential to the semiconductor substrate, applies a second potential to the electrode member, and applies a third potential to the one of the electrode films. The second potential is lower than the first potential. The third potential is lower than the second potential.

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Toyota, Japan

Shinya Naito