Renesas Electronics Corporation

Shinya Miyazaki

Katsumi Dosaka

Fukashi Morishita

Naoya Watanabe

Mihoko Akiyama

Isamu Hayashi

Teruhiko Amano

Kenji Yoshinaga

Masakazu Ishibashi

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Content addressable memory with reduced power consumption and increased search operation speed

Content addressable memory

Growing community of inventors

Kodaira, Japan

Shinya Miyazaki