Ricoh Company, Ltd.

Ps4 Luxco S.a.r.l.

Elpida Memory, Inc.

Shinya Miyazaki

Yuji Takahashi

Hiroyuki Kawamoto

Yasuyuki Nomizu

Hiroaki Fukuda

Yoshiyuki Namizuka

Hideto Miyazaki

Sugitaka Oteki

Fumio Yoshizawa

Takeharu Tone

Rie Ishii

Takako Satoh

Chiaki Dono

Takenori Sato

Chikara Kondo

Taihei Shido

Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

Semiconductor device having output buffer circuit in which impedance thereof can be controlled

A device that includes first and second buffer circuits electrically connected to a terminal and an output control circuit activating the first buffer circuit and deactivating the second buffer circuit in a first state and activating one of the first and second buffer circuits and deactivating the other of the first and second buffer circuits based on input data in a second state. The output control circuit is brought into one of the first and second states.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

Semiconductor device having serializer converting parallel data into serial data to output serial data from output buffer circuit

Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.

Semiconductor device performing burst order control and data bus inversion

A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Semiconductor device generates complementary output signals

The image processing device comprises a first function block section formed of functional blocks which require a supply of power so as to maintain the image processing device in an operating state when the power supply is on, and a second function block section formed of functional blocks which need not be supplied with the power so as to maintain the image processing device in an operating state even when the power supply is on. The supply of power to the second function block section can be stopped when desired, while continuing the supply of power to the first function block section, thereby saving the power.

Image processing device, method for saving power consumption of the image processing device, and a computer product

A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Method and apparatus for image processing, and a computer product

The image processing apparatus comprises an image data control section and a system controller. The image data control section is connected to any one or more of a sensor board unit, an image-memory access control section, an image processor, a video data control section, and a facsimile control unit. The system controller switches, when the image data to be transmitted to the image data control section conflicts with one another, a transmission mode of the image data in conflict with one another. Further, the image-memory access control section and the image processor share jobs of performing image processing on the image data.

Method and apparatus for image processing method, and a computer product

An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Image processor

The image processor comprises a switch that divides image data into m&#xd7;n pixels, having n lines with m pixels per one line; a group of line memories that store the divided image; a compression device which batch compresses the image data of m&#xd7;n pixels. Further, a command control unit provides control so as to send the (n&#x2212;1) lines of image data among m&#xd7;n pixels of image data to the group of line memories, and the remaining one line of image data directly to the compression device, and to send the m&#xd7;(n&#x2212;1) pixels of image data stored in the line memories to the compression device.

Image processor including a data compression unit having a switch and image processing method thereof

The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.

Documents are read and the read image data and the information about the size of the document is stored in a memory. A factor of enlargement/reduction is calculated based on the stored size information. An image processorinterpolates the image data based on the calculated enlargement/reduction factor and reproduces the enlarged/reduced document.

Apparatus and method for processing images, and computer product

The image processing apparatus comprises a reading unit which simultaneously reads image data from two, an obverse and a reverse, surfaces of a document, and a compressing unit which compresses received image data. The apparatus further comprises a controlling unit which orchestrates a flow of image data from the reading unit to the compressing unit in such a manner that the image data corresponding to the obverse surface and the reverse surface is input into the compressing unit at different timing.

Image processing apparatus

An image processing apparatus is connected to a plurality of functional units including an image processor which processes images. A process controller provides control over the entire operation. A ROM previously stores information about the content of the image processing. The process controller reads the information stored in the ROM and transfers this information in a host buffer provided with the image processor. The image processor processes the image data based on the information stored in the host buffer.

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Tokyo, Japan

Shinya Miyazaki