Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electric Industrial

Shinya Miyaji

Nobuo Higaki

Shuichi Takayama

Masato Suzuki

Tetsuya Tanaka

Taketo Heishi

Kensuke Odani

Nobuki Tominaga

Hiroshi Kamiyama

Hajime Ogawa

Kenichi Kawaguchi

Akira Tanaka

Toru Morikawa

Seiichi Urushibara

Kazushi Yamamoto

Yoshito Nishimichi

Atsushi Ubukata

Satoshi Ogura

The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

Variable address length compiler and processor improved in address management

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR

Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions

An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.

A processor for executing operations based on instructions includes an operation constant register,, a branching constant register,, a decoding unit,for decoding an instruction stored in an instruction register,, a constant register control unit,, and an execution unit,. When the decoding unit,finds that the instruction includes a constant to be stored in the branching constant register,, the constant register control unit,shifts a present value in the branching constant register,and inserts the constant to be stored, thereby storing a new constant in the branching constant register,. When the decoding unit,finds that a constant is to be stored in the operation constant register,, the constant register control unit,shifts the present value in the operation constant register,and inserts the constant to be stored, thereby storing a new constant in the operation constant register,. When the decoding unit,finds that the instruction includes a branch operation, the execution unit,executes the branch operation using the constant stored in the branching constant register,. When the decoding unit,finds that the instruction includes an arithmetic operation, the execution unit,executes the arithmetic operation using the constant stored in the operation constant register

Constant reconstruction processor that supports reductions in code size and processing time

In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

Apparatus and method for processing data with a plurality of flag groups

A processor for decoding and executing an instruction includes: an instruction register,for storing an instruction; a format decoder,for decoding a format code located in the P,field,of the instruction stored in the instruction register,; a constant storage unit including a storage region; a constant register control unit,which, when the format decoder,has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register,, transfers the constant from the instruction register,to the constant storage unit,; and a constant register output unit,which, when the format decoder,has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register,with the piece of the operand.

Constant reconstructing processor that execute an instruction using an operand divided between instructions

A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.

Processor which returns from a subroutine at high speed and a program translating apparatus which generates machine programs that makes a high-speed return from a subroutine

The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an execution of a program, and has a debug function with a necessary minimized break determinator included in a chip. A part of the break conditions in a sequence is set in an external break determinator. The remaining condition other than the part of the conditions is set in an internal break determinator. While monitoring an operation status of a processor executing a program, when the conditions set in the external break determinator are satisfied, a break enable signal is input to an AND logic circuit via a break enable input terminal and is held. When the break determinator detects the satisfaction of the remaining condition stored in the internal break determinator, a break signal is supplied from the AND logic circuit to the CPU, thereby breaking the program without delay.

Debug apparatus

A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

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Hirakata, Japan

Shinya Miyaji