Honda Motor Co., Ltd.

Shinya Maita

Satoshi Hasegawa

Hitoshi Saito

Shigeto Akahori

Yoshinari Tsukada

Yasuhiro Maeda

Yoko Yamaji

Genki Nakamura

Yuki Negoro

Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an ndrain layer; a parallel pn layer including ndrift and p pillar layers joined alternately; a composite layer including a p base layer and an nsource layer, the ndrain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the nsource layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the ndrift layer.

BiMOS semiconductor device

Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application deviceis configured to have a contacting section having a plurality of projectionsfor contacting a contact regioninside an active regionof a semiconductor elementand applying the test current thereto, and a pressing sectionwhich presses the contacting sectionagainst the semiconductor elementsuch that each projectioncontacts the contact region. A plurality of the projectionsare arranged such that an arrangement density of outside projectionsis larger than the arrangement density of inside projections

Current application device and manufacturing method of semiconductor element

Growing community of inventors

Wako, Japan

Shinya Maita