Renesas Electronics Corporation

Nec Electronics Corporation

Shinya Konishi

Kan Takeuchi

Masaki Shimada

Norio Arai

Fumio Tsuchiya

Daisuke Oshida

Naoya Ota

Yoshio Takazawa

Osamu Ohnishi

A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.

Semiconductor device, electronic device and electronic system

An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.

Semiconductor device and semiconductor system

The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.

Semiconductor device and analysis system

A communication device includes a current information storage unitthat stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unitthat takes in and stores a signal stored in the current information storage unitwhen a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unitthat selects CLKSELused for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unitwhen a variation point of the reception signal is detected, and selects CLKSELbased on a signal stored in the past information storage unitwhen no variation point of the reception signal is detected.

Communication device

A communication apparatus including a clock generation circuit outputting a plurality of clocks, each clock having a different phase from the other, a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving the payload, sampling the sync word by using each of the plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling the sync word successfully, the synchronization detection block being capable of sampling the payload by using a clock or clocks, a clock phase selection block coupled to the synchronization detection block to receive the first signal, and a clock gate unit to receive each of the plurality of clocks and the second signal to output the selected one of the plurality of clocks, and not to output a rest of the plurality of the clocks based on the second signal.

Communication apparatus

There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection blockwhich detects synchronization by performing a receiving process using a plurality of clocks whose phase differs from each other with respect to synchronization information contained in a first frame as well as identifies the synchronization detected clocks as candidate clocks to be selected; a clock phase selection blockwhich selects a sampling clock to be used for sampling of the transmission signal from the candidate clocks to be selected, selects a stop clock separated by a predetermined phase from the selected sampling clock, and outputs an instruction for the stop clock; and a clock gate unitwhich, terminates supplying the stop clock from the plurality of clocks to the synchronization detection blockas well as supplies other clocks to the synchronization detection block. In the process of receiving a second frame following the first frame, the synchronization detection blockdetects synchronization from the clocks other than the stop clock.

The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.

Synchronous circuit and method for receiving data

A nonvolatile semiconductor memory includes a memory cell array and a replacement data cell array. The memory cell array includes a plurality of main cell arrays and a plurality of redundancy cell arrays. The replacement data cell array stores a replacement data indicating a replacement of one main cell array by one redundancy cell array. The replacement data cell array includes a plurality of first storage sections and a plurality of second storage sections. The first storage section corresponds to one redundancy cell array and stores a replacement confirmation data indicating whether or not the corresponding one redundancy cell array replaces one main cell array, by nonvolatile memory cells of two bits. The second storage section corresponds to one redundancy cell array and stores an address data indicating an address for one main cell array which is replaced by the corresponding one redundancy cell array.

Growing community of inventors

Kanagawa, Japan

Shinya Konishi