Kioxia Corporation

Toshiba Memory Corporation

Shinya Koizumi

Kiyotaka Iwasaki

Kouji Watanabe

A memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.

Memory system

A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Memory system and method of controlling a memory chip

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Memory controller

A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Memory system executing calibration on channels

A memory system includes a first memory chip, and a controller that includes a first circuit, a second circuit, and a third circuit. The third circuit is configured to manage a first differential power consumption value that is a difference between first and second power consumption values. The first power consumption value is on first power that the first memory chip consumes while executing a first operation. The second power consumption value is on second power that the first memory chip consumes when suspending the first operation. The third circuit is configured to determine whether causing the first memory chip to suspend the first operation to execute a second operation is possible based on the first differential power consumption value.

Growing community of inventors

Kamakura Kanagawa, Japan

Shinya Koizumi