Fujitsu Corporation

Shinya Kato

Takumi Nonaka

Toshiyuki Muta

Jin Takahashi

Takayuki Shimamura

Takato Noda

Takayoshi Kyono

Takashi Terunuma

Ryuichi Nisiyama

A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.

Device and method for synchronous data transmission using reference signal

A cache control apparatus for an information processing system having a cache memory with a plurality of ways is disclosed, in which the hardware amount is reduced and the delay of the response time is minimized. At the time of cache access, each way is indexed by time division, and when updating the cache, a way to be updated is designated thereby to update the cache tag and the cache data. The data indexed by time division can be judged for a hit each time of indexing or alternatively, the data of all the ways are judged for a hit after being held in a buffer. The data indexed by time division is sent to the reader as response without regard to the way, and when a miss is judged, a cancel signal is sent thereby to minimize the access time delay. Further by predicting the address of a way, the access time can be further improved.

Cache control apparatus for a microprocessor

To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.

Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method

A cache memory device by which a processing speed can be elevated and which comprises a primary cache memory containing two primary ways of WAY and WAY each retaining a bit LRU and a bit LRU taking either a value or together with data and an address, a primary old way determining circuit for determining, on the basis of patterns of the bit LRU and the bit LRU which is an old way retaining data which has not been accessed for the longest period of time in the primary ways WAY and WAY and a primary cache control circuit inverting only the bits (the bit LRU or the bit LRU ) retained in the old way which has been accessed.

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Kawasaki, Japan

Shinya Kato