Nagoya University

Seiko Epson Corporation

Other

Toyota Jidosha Kabushiki Kaisha

Sumitomo Electric Industries, Limited

Sumitomo Wiring Systems, Limited

Autonetworks Technologies, Limited

Shinya Honda

Hiroaki Takada

Akinari Todoroki

Katsuya Tanaka

Hiroshi Ueda

Hideyuki Iwakiri

Ryo Kurachi

Akihiko Tamura

Kazuhiro Kajio

Yutaka Matsubara

In an on-vehicle system, on-vehicle device and gateway are connected via a first network, and the gateway and relay are connected via a second network. The relay performs open-close control of a gate, using a TAS standard of Ethernet TSN. The gateway receives first and second packets including given data, generates a third packet including the first and second packets, and sends the third packets at the transmission timing that is a timing the gate is placed in from closed state to open state to the relay. The relay receives the third packet from the gateway. The relay switches timing to transfer data, for each type of data, and transfer the third packet to the other relay, during a period in which the gate for the type of data is in an open state.

On-vehicle system, gateway, relay, non-transitory computer-readable medium storing program, information processing method, information processing system, and vehicle

Provided are a communication device and a communication restriction program capable of suppressing invalid message transmission to a network by injecting an invalid program. The ECU includes a CAN controller having a register group storing a value concerning communication with a different ECU and a processing unit processing a value for the register group. The ECU switches the mode between the full control mode in which writing and reading are allowed for the register group in the CAN controller and the restriction mode wherein writing and reading are restricted for a part of the registers in the register group. The ECU sets a predetermined period from activation corresponding to the full control mode, and switches the full control mode to the restriction mode after the predetermined period elapses. After switching to the restriction mode, the ECU will not switch the mode to the full control mode.

Communication device and non-transitory recording medium

A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the schedule.

Processor and interrupt controlling method

To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor Pof the unit processors Pto Pcomprises an purge inhibit flagfor causing the unit processor Pto enter a lock state where the purge of the task is being inhibited, a hardware semaphore unitfor inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor Pafter the unit processor Pis brought into the lock state, and an interrupt control unitfor inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

Parallel processing device and exclusive control method

Growing community of inventors

Nagoya, Japan

Shinya Honda