Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Hitachi, Ltd.

Windbond Electronics Corp.

Winbond Electronics Corporation

Socionext Inc.

Shinya Fujioka

Kotoku Sato

Hitoshi Ikeda

Yasuharu Sato

Takaaki Suzuki

Koichi Nishimura

Tomohiro Kawakubo

Yoshiaki Okuyama

Akihiro Funyu

Masao Taguchi

Tadao Aikawa

Katsuhiro Mori

Yoshitaka Takahashi

Kota Hara

Waichiro Fujieda

Toshiya Uchida

Jun Ohno

Kimiaki Satoh

Yasurou Matsuzaki

Waichirou Fujieda

Takayuki Nagasawa

Kaoru Mori

Masahiko Mizutani

Yasuyuki Eguchi

Takahiro Sawamura

Hiroyoshi Tsuboi

Hiroyuki Kobayashi

Yoshihiro Ashi

Shinichi Yamada

Atsushi Hatakeyama

Masato Matsumiya

Toru Koga

Masahiro Niimi

Hiroyoshi Tomita

Hirohiko Mochizuki

Tatsuya Kanda

Masaki Okuda

Yoshimasa Yagishita

Shusaku Yamaguchi

Takumi Oishi

Nobumi Kodama

Akihiko Sugata

Yoshihide Bando

Kenji Fujihira

Masao Niibe

Yasuhiro Takada

Tatsuhiro Watanabe

Masahiro Yada

Kazuhiro Ninomiya

Atsushi Sukeno

Koutoku Sato

Shinichiro Suzuki

Kohji Nozoe

Akihiro Funya

Toru Miyabo

Tsuzumi Ninomiya

A semiconductor memory device that can easily recognize the content of errors in data is provided. The semiconductor memory device includes a memory cell array, an error detection and correction circuit, and an input/output circuit. The memory cell array includes a plurality of memory cells. The error detection and correction circuit detects and corrects error bits included in the data output by the memory cell array. The error detection and correction circuit activates an error detection signal when the data includes a correctable error bit. The input/output circuit stops the clocking of the data strobe signal output with data when the data includes uncorrectable error bits.

Semiconductor memory device and method of reading a semiconductor memory device

A semiconductor memory device capable of suppressing an increase in power consumption and avoiding data destruction due to the row hammer problem is provided. The semiconductor memory device includes a refresh control unit (first control unit) that sets a memory cell refresh interval based on information about a memory cell refresh interval included in a predetermined command input from the outside.

Semiconductor memory device having control unit which sets the refresh interval of the memory cell

A memory device and a method for input/output buffer control are provided. The memory device includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input/output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to an operation mode of the memory device, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.

Memory device and method for input and output buffer control thereof

A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, and the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to a sequence of receiving the page starting addresses.

Memory apparatus and burst read and burst write method thereof

A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Dynamic random access memory with reduced power consumption

In a semiconductor device that generates a power supply voltage from an RF carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. The limiter circuits and the diodes are connected in parallel between the capacitors connected to the antenna connection terminal and a node supplied reference potential VSS of the power supply voltage.

Semiconductor device including a rectification circuit

A transmission network system includes a network terminating device connected to a user terminal and an authentication information device connected to the network terminating device through a transmission network. The transmission network is connected to a reference clock that holds a reference time. The network terminating device includes a terminating internal clock that synchronizes with the reference clock, when receiving a first frame from the user terminal, generates a second frame including a time outputted from the terminating internal clock as a request time on the basis of the first frame, and transmits the second frame to the authentication information device. The authentication information device generates time authentication information based on the request time included in the received second frame, generates a third frame including the generated time authentication information, and transmits the third frame to the transmission network.

Transmission network system, transmission method, and authentication information device

A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus linesprovided respectively associated with the plurality of memory blocks; a plurality of input/output ports; a selectorselectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unitsetting a connection of the selector.

Semiconductor memory device and electronic device

When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.

Semiconductor memory device and control method thereof

A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.

Semiconductor memory device comprising a plurity of input/output ports and a plurity of memory blocks corresponding to the plurality of input/output ports

When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.

Transfer apparatus, transfer network system, and transfer method

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Semiconductor memory device and method of controlling the same

A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.

Packet transfer system, network management apparatus, and edge node

When a neighbor ONU receives a signal with light intensity high enough to secure communication between an OLT and a remote ONU, the light intensity may be excessively high to damage a receiver of the neighbor ONU. In order to avoid such a problem, each ONU is notified of a downstream signal transmission plan (downstream light intensity map) prior to transmission of a downstream signal. Each ONU receives the downstream light intensity map (light intensity transmission schedule of downstream signal) in advance. Thus, the neighbor ONU can block or attenuate an optical signal addressed to the remote ONU, and the remote ONU can determine normal operation even when the remote ONU cannot receive a signal addressed to the neighbor ONU. Thus, the remote ONU can be prevented from issuing a wrong error signal.

Passive optical network system

The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal circuit and operates according to a second power supply voltage, a first control unit that includes a control input/output circuit, coupled to the memory input/output circuit and operates according to the second power supply voltage, a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal, a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal, and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

Memory system and method that changes voltage and frequency

Growing community of inventors

Kawasaki, Japan

Shinya Fujioka