Fujitsu Corporation

Shinya Aiso

Noriyuki Tokuhiro

Keiji Shimatani

Toshiaki Ozawa

Noriyuki Takahashi

An information processing apparatus configured to adjust a phase relation between a data signal and a strobe signal includes a processor and memory. The memory stores instructions for causing the processor to execute identifying, for each of a plurality of candidates for reference values used to perform a determination regarding a value of the data signal, at least one phase difference between the data signal and the strobe signal for successfully acquiring the data signal according to the strobe signal, determining a reference value of the plurality of candidates for which a period for successfully acquiring the data signal is longer than periods for any other candidates based on the identified phase difference for each candidate, and adjusting the phase relation between the data signal and the strobe signal based on the period for the determined reference value.

Information processing apparatus, information processing system and phase adjusting method

A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a second address of the memory after a write operation of the first dummy pattern by the first write circuit; a third write circuit configured to write a second dummy pattern including a plurality of consecutive second dummy values at a third address of the memory after a write operation of the first pattern by the second write circuit; a read circuit configured to read the written first pattern based on the second address of the memory; and a timing adjustment circuit configured to adjust a timing at which data is written into the memory based on a read first pattern.

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Kawasaki, Japan

Shinya Aiso