Fujitsu Corporation

Shintaro Itozawa

Junji Ichimiya

Hiroshi Nakayama

Daisuke Itou

Takayuki Kinoshita

Koichi Odahara

A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

Transmission device, receiving circuit and control method of transmission device

A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.

Information processing apparatus, data reception device and method of controlling the information processing apparatus

A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.

Data transfer unit, data transmission device, data receiving device, and control method

A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.

Information processing device, data transmitting device, and data transfer method of data transmitting device

When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device.

Data processing system having multiplexed data relaying devices, data processing aparatus having multiplexed data relaying devices, and a method of incorporating data relaying devices in data processing system having multiplexed data relaying devices

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Kawasaki, Japan

Shintaro Itozawa