Semiconductor Energy Laboratory Co., Ltd.

Shintaro Harada

Yoshiyuki Kurokawa

Takeshi Aoki

Takayuki Ikeda

Hiroki Inoue

Shunpei Yamazaki

Hidetomo Kobayashi

Takashi Nakagawa

Yusuke Negoro

Roh Yamamoto

Kiyotaka Kimura

Kei Takahashi

Koji Kusunoki

Munehiro Kozuma

Yuki Okamoto

Yosuke Tsukamoto

Katsuki Yanagawa

Shuji Fukai

Tatsunori Inoue

Fumika Akasawa

Sho Nagao

An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

Imaging device and electronic device

A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

Logic circuit formed using unipolar transistor, and semiconductor device

The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which 'H' is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.

Detecting device and semiconductor device

A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

Neural network semiconductor device and system using the same

An electronic device capable of efficiently recognizing a handwritten character is provided. The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.

Touch panel system, electronic device, and semiconductor device having a neural network

A semiconductor device capable of efficiently recognizing images utilizing a neural network is provided. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores a parameter of a filter. The shift register group captures image data and outputs part of the image data to the D/A converter while shifting the image data. The D/A converter converts the part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.

Semiconductor device having neural network

Novel connection between neurons of a neural network is provided. A perceptron included in the neural network includes a plurality of neurons; the neuron includes a synapse circuit and an activation function circuit; and the synapse circuit includes a plurality of memory cells. A bit line selected by address information for selecting a memory cell is shared by a plurality of perceptrons. The memory cell is supplied with a weight coefficient of an analog signal, and the synapse circuit is supplied with an input signal. The memory cell multiplies the input signal by the weight coefficient and converts the multiplied result into a first current. The synapse circuit generates a second current by adding a plurality of first currents and converts the second current into a first potential. The activation function circuit is a semiconductor device that converts the first potential into a second potential by a ramp function and supplies the second potential as an input signal of the synapse circuit included in the perceptron in a next stage.

Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit

An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor. Switching on/off states of the first to third transistors achieves intermittent driving of the semiconductor device.

Electronic device

Provided is a semiconductor device in which leakage current due to miniaturization of a semiconductor element is reduced and delay at a time of context switch of a multi-context PLD is reduced. A first transistor and a second transistor included in a charge retention circuit functioning as a configuration memory each include an oxide semiconductor in a semiconductor layer serving as a channel formation region. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is connected to a switch for context switch. In the switch used for context switch, electrostatic capacitance on an input side to which the one of the source and the drain of the second transistor is connected is larger than electrostatic capacitance on an output side.

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Kanagawa, Japan

Shintaro Harada