Sumitomo Mitsubishi Silicon Corporation

Sumco Corporation

Sumitomo Metal Industries, Inc.

Shinsuke Sadamitsu

Masataka Hourai

Nobumitsu Takase

Koji Sueoka

Makoto Ito

Yasuo Koike

Takayuki Kihara

Hideshi Nishikawa

Masataka Horai

Hiroyuki Takao

Kazunari Kurita

Wataru Sugimura

Shigeru Umeno

Eiichi Asayama

Naoshi Adachi

Masakazu Sano

Masanori Akatsuka

Kouji Sueoka

Masaharu Ninomiya

Koujl Sueoka

Tsuyoshi Kubota

Tooru Nagashima

Takeshi Kii

Hisashi Katahama

Disclosed are high resistivity silicon wafers, wherein the interstitial oxygen concentration thereof is 8&#xd7;10atoms/cm(ASTM F121-1979) or less, BMD (Bulk Micro Defect) density&#x2014;oxygen precipitate within wafer&#x2014;is 5&#xd7;10pieces/cmor less, and an electric resistivity thereof is 100 &#x3a9;&#xb7;cm or more. And further disclosed are high resistivity silicon wafers having an electric resistivity of 100 &#x3a9;&#xb7;cm or more, which are cut from crystal region where no COP (Crystal Originated Particle) exist, and in which neither COP (Crystal Originated Particle) nor oxygen precipitate exist at the area from wafer surface to the depth of 5 &#x3bc;m or more owing to high temperature treatment. It is preferable that, in said high resistivity wafers, carbon concentration in wafers is 1&#xd7;10atoms/cmor more (ASTM F123-1981), and/or nitrogen concentration is 1&#xd7;10atoms/cmor more. Accordingly, high resistivity silicon wafers are provided, wherein the mechanical strength thereof is highly secured, and an excellent characteristic to slip generation is provided, so as to be optimal for base wafers of silicon wafers having a SOI structure or an epitaxial structure.

High resistivity silicon wafers

By using oxygen-containing silicon wafers obtained by the CZ method and by combining the first heat treatment comprising controlled heat-up operation (ramping) with the second heat treatment comprising high-temperature heat treatment and medium temperature heat treatment in accordance with the process for producing high-resistance silicon wafers according to the present invention, it is possible to obtain high-resistance silicon wafers capable of maintaining their high resistance even after heat treatment in the process of device manufacture while efficiently inhibiting the formation of oxygen donors and preventing changes in resistivity. Further, excellent epitaxial wafers and SOI wafers can be produced using those high-resistance silicon wafers and, therefore, they can be applied in a wide field including high-frequency communication devices and analog/digital hybrid devices, among others.

Process for producing high-resistance silicon wafers and process for producing epitaxial wafers and SOI wafers

There is obtained a silicon wafer which has a large diameter, where no slip generated therein in a wide range of a density of oxygen precipitates even though a heat treatment such as SLA or FLA is applied thereto, and which has high strength. First, by inputting as input parameters combinations of a plurality of types of oxygen concentrations and thermal histories set for manufacture of a silicon wafer, a Fokker-Planck equation is solved to calculate each of a diagonal length L and a density D of oxygen precipitates in the wafer after a heat treatment step to form the oxygen precipitates () and immediately before a heat treatment step of a device manufacturing process is calculated. Then, a maximum heat stress S acting in a tangent line direction of an outer peripheral portion of the wafer in the heat treatment step of the device manufacturing process is calculated based on a heat treatment furnace structure and a heat treatment temperature used in the heat treatment step of the device manufacturing process, and then an oxygen concentration or the like satisfying the following Expression (1) is determined:12000&#xd7;&#x2003;&#x2003;(1).

Method for manufacturing silicon wafer method

A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900&#xb0; C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050&#xb0; C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 &#x3a9;cm or more, an oxygen concentration is 14&#xd7;10atoms/cm(ASTM F-121, 1979) or more and a carbon concentration is 0.5&#xd7;10atoms/cmor more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12&#xd7;10atoms/cm(ASTM F-121, 1979) or less. Thus, there is provided a high-resistance, low-oxygen and high-strength silicon wafer in which resistivity is 100 &#x3a9;cm or more and an oxygen precipitate (BMD) having a size of 0.2 &#x3bc;m is formed so as to have high density of 1&#xd7;10/cmor more.

High resistance silicon wafer and its manufacturing method

A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100&#xb0; C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 &#x3a9;cm or more and a carbon concentration is 5&#xd7;10to 5&#xd7;10atoms/cmso that a remaining oxygen concentration becomes 6.5&#xd7;10atoms/cmor more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.

High-resistance silicon wafer and process for producing the same

A high resistivity p type silicon wafer with a resistivity of 100 &#x3a9;cm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 &#x3bc;m from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.

High resistivity silicon wafer and method for fabricating the same

To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 &#x3a9; cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from &#x2212;5 to 50 ppta method in terms of (a donor concentration&#x2014;an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from &#x2212;25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used. Alternatively, a silicon crystal manufactured with a CZ method or a MCZ method using poly-silicon raw material is used.

Manufacturing method of high resistivity silicon single crystal

In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Evaluation method of IG effectivity in semiconductor silicon substrates

There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1&times;10 atoms/cm or more, or with nitrogen doping at a concentration of 1&times;10 atoms/cm and carbon doping at a concentration of 0.1&times;10 &minus;5&times;10 atoms/cm and/or boron doping at a concentration of 1&times;10 atoms/cm or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment.

Silicon single crystal, silicon wafer, and epitaxial wafer.

A method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device by which a gettering ability can be given to an epitaxial wafer in which the formation of BMD is not able to be expected in both low- and high-temperature device manufacturing processes, with the manufacturing processes being lower and higher than 1,050&deg; C. in temperature, and has a specific resistance of &gE;10 m&OHgr;&middot;cm. When this method is used, such BMD that is sufficient to obtain gettering can be formed in both the low- and high-temperature processes, with the manufacturing processes being lower and higher than 1,050&deg; C. in temperature, even in the epitaxial wafer having a specific resistance of &gE;10 m&OHgr;&middot;cm by performing low-temperature heat treatment at 650&tilde;900&deg; C. before starting epitaxial film formation, by selecting the heat-treating time in accordance with the process temperature in the device manufacturing processes and heavy-metal contaminants which are mixed in during the device manufacturing processes can be gettered sufficiently. Therefore, the characteristic deterioration of a device can be prevented and the yield of the device can be improved.

Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device

An object of the present invention is to provide a single-crystal silicon wafer where octahedral voids of Grown-in defects, which are the generation source of COP on the surface and COP at several .mu.m depth of the surface layer of the single-crystal silicon wafer grown by the CZ method, are effectively eliminated, and a fabrication method of this wafer, where oxygen near the surface is out-diffused by annealing in a hydrogen and/or inactive gas ambient and oxide film on the inner walls of the octahedral voids near the surface are removed by the created unsaturated oxygen area, then oxidation annealing is performed in an oxygen ambient or mixed gas ambient of oxygen and inactive gas, so that interstitial silicon atoms are forcibly injected to completely eliminate the octahedral voids near the surface, and at the same time an IG layer is created in the bulk of the wafer.

Growing community of inventors

Tokyo, Japan

Shinsuke Sadamitsu