Fuji Electric Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Kabushiki Kaisha Toshiba

Sanyo Electric Co., Ltd.

Other

Sumitomo Electric Industries, Limited

National Institute of Advanced Industrial Science

Shinsuke Harada

Yusuke Kobayashi

Kenji Fukuda

Noriyuki Iwamuro

Mitsuo Okamoto

Naoyuki Ohse

Manabu Takei

Takahito Kojima

Yasuyuki Hoshi

Akimasa Kinoshita

Yuichi Harada

Junji Senzaki

Tsutomu Yatsuo

Ryosuke Iijima

Yasunori Tanaka

Yasuhiko Oonishi

Shinya Kyogoku

Ryoji Kosugi

Seiji Suzuki

Shinichi Kimoto

Kazuhiro Adachi

Masakazu Baba

Makoto Utsumi

Masanobu Iwaya

Katsuhisa Tanaka

Naoki Kumagai

Takashi Tsutsumi

Takeshi Tawara

Yoshiyuki Sakai

Keiko Ariyoshi

Atsushi Tanaka

Kazuo Arai

Makoto Katou

Makoto Kato

Tatsuo Shimizu

Takeyoshi Masuda

Takashi Shinohe

Hiromu Shiomi

Tsunehiro Nakajima

Fumikazu Imai

Takumi Fujimoto

Tsuyoshi Araoka

Kazutoshi Kojima

Tomoaki Hatayama

Youichi Makifuchi

Yoshiyuki Sugahara

Mitsuru Sometani

Kensuke Takenaka

Satoshi Kuroda

Ryouji Kosugi

A semiconductor device having a connecting region between an active region and an edge region. The semiconductor device including a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, a second semiconductor layer provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layer, a plurality of first and second trenches penetrating through the first semiconductor regions and the second semiconductor layer, a plurality of gate electrodes provided in the first trenches, via a plurality of gate insulating films, respectively, and a plurality of Schottky electrodes respectively provided in the second trenches. The semiconductor substrate, the first and second semiconductor layers, the first semiconductor regions, the first trenches, the gate electrodes and the gate insulating films are provided in the active region. The second trenches and the Schottky electrodes are provided in both the active region and the connecting region.

Semiconductor device

A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator

A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×10cm.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.

A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layerof a second conductivity type on a front surface of a silicon carbide semiconductor substrateof a first conductivity type and selectively forming semiconductor regionsof the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

Super junction silicon carbide semiconductor device and manufacturing method thereof

A semiconductor device capable of suppressing forward voltage degradation and loss during turn-on. A vertical MOSFET includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, third semiconductor regions of the second conductivity type, first trenches and second trenches, gate electrodes provided in the first trenches via a gate insulating film, and Schottky metal provided in the second trenches. In a region between an active region through which current flows during an on-state and an edge region that surrounds a periphery of the active region and sustains a breakdown voltage, sidewalls of the second trenches are apart from the second semiconductor regions and the third semiconductor regions.

Semiconductor device including vertical MOSFET and Schottky barrier diode

At a front surface of a silicon carbide base, an n−-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode, and a barrier metal is provided in the trench on the interlayer insulating film.

Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench

One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrateof a first conductivity type, a first semiconductor layerof the first conductivity type, a second semiconductor layerof a second conductivity type, first semiconductor regionsof the first conductivity type, first trenchesand a second trench, gate electrodesprovided in the first trenchesvia a gate insulating film, and a Schottky electrodeprovided in the second trench. The first trenchesare provided in a striped pattern, in a plan view and the second trenchsurrounds the first trenches

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

Semiconductor device, inverter circuit, drive device, vehicle, and elevator

A vertical MOSFET having a trench gate structure includes an n-type drift layer and a p-type base layer formed by epitaxial growth. In n-type drift layer, an n-type region, a lower second p-type region and a first p-type region are provided. A part of the lower second p-type region extends in a direction opposite that of a depth of the trench and is connected to the p-type base layer.

A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

A vertical MOSFET having a trench gate structure includes an n-type drift layer and a p-type base layer formed by epitaxial growth. In n-type drift layer, an n-type region, a lower second p-type region and a first p-type region are provided. A part of the lower second p-type region extending in a direction opposite that of a depth of the trench and connected to the p-type base layer.

A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.

A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 &#x3bc;m and smaller than 1.0 &#x3bc;m.

Silicon carbide semiconductor element and method of manufacturing silicon carbide semiconductor

Growing community of inventors

Tsukuba, Japan

Shinsuke Harada