Sharp Kabushiki Kaisha Corporation

Shinsuke Anzai

Yasumichi Mori

Manabu Yumoto

Masayuki Ehiro

Shunsuke Nagasawa

Takahiko Yoshimoto

Masayuki Miyamoto

Hiroaki Fujino

Masahiko Watanabe

Takeshi Nojima

Shinichi Yoshida

Toshio Watanabe

Kengo Takahama

Hidehiko Tanaka

Kenji Kamei

Masafumi Katsutani

Shunichi Murahashi

Hirofumi Matsui

Masami Mori

Yoshihiro Nakatani

Munetaka Masaki

Kohichi Hosokawa

A touch panel system () includes a touch invalidating section () which, in a case where a specific point of the sensor panel () is continuously touched for a predetermined period of time, invalidates an instruction given, in accordance with the touch, to a host computer (). Furthermore, the touch invalidating section () invalidates an instruction corresponding to a next touch on the point.

Touch sensor system and electronic device

A touch panel system prevents an incorrect operation caused by an unintended contact of an object with a touch panel while suppressing a decline in sensitivity of detection of presence or absence of a touch on the touch panel. The touch panel system includes a touch invalidating section which, in a case where a specific point of a touch panel is continuously touched for a predetermined period of time, invalidates an instruction that is given, in accordance with the touch, to an electronic device including the touch panel.

Touch panel system and electronic device

A touch panel system () prevents an incorrect operation caused by an unintended contact of an object with a touch panel while suppressing a decline in sensitivity of detection of presence or absence of a touch on the touch panel. The touch panel system () includes a touch invalidating section () which, in a case where a specific point of a touch panel () is continuously touched for a predetermined period of time, invalidates an instruction that is given, in accordance with the touch, to an electronic apparatus including the touch panel ().

Touch panel system and electronic apparatus

A driving circuit of at least one embodiment includes: m output terminals; m+1 video signal output sections including m+1 output circuits, respectively; a decision section for determining the quality of each of the video signal output sections; and switches for switching connections between the output terminals and the video signal output sections in accordance with a result of determination made by the decision section. When the decision section has determined the ith (i being a natural number of m or less) video signal output section to be defective, the switches connect the jth (j being a natural number of i&#x2212;1 or less) video signal output section to the jth output terminal and connect the (k+1)th (k being a natural number of i or more to m or less) video signal output section to the kth output terminal. Thus provided is a driving circuit, capable of self-repairing a defective one of the video signal output sections, which has more simplified wires connected to the video signal output sections.

Drive circuit and display device

In one embodiment of the present invention, a liquid crystal driving semiconductor IC for driving a display panel includes an output terminal connected to the display panel, an output circuit block including a DAC circuit, and a spare output block including a DAC circuit, the DAC circuits and being connectable to the output terminal. The IC includes an op amp for comparing output signal from the DAC circuit with that of the DAC circuit, and judging circuit for judging, based on the comparison result of the op amp, whether the DAC circuit is defective, and switches and for, if the DAC circuit is defective, connecting the spare DAC circuit to the output terminal in replacement of the defective DAC circuit. This provides an IC for driving a display device, which IC has concrete measures to easily detect a defect in an output circuit, and can perform self-healing for the defect in the output circuit.

Display device and television system including a self-healing driving circuit

In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.

Semiconductor memory device

Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

Bias voltage applying circuit and semiconductor memory device

A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.

Nonvolatile semiconductor memory device

A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.

A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

Reading circuit, reference circuit, and semiconductor memory device

A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.

Growing community of inventors

Tenri, Japan

Shinsuke Anzai