Hitachi, Ltd.

Other

Hitachi Ulsi Systems Co., Ltd.

Nippon Hoso' Kyokai

Shinobu Torikoshi

Kenji Katsumata

Shigeru Komatsu

Keisuke Inata

Masuo Oku

Takaaki Matono

Hironori Komi

Masaaki Hisanaga

Fumihito Tanaka

Ryosuke Toya

Shigeru Hirahata

Toshinori Murata

Sunao Suzuki

Nobufumi Nakagaki

Yumi Bando

Takayuki Mori

Yuichi Ninomiya

Takanori Eda

Haruki Takata

Takumi Okamura

Noboru Kojima

Koichi Yamaguchi

Toshiyuki Sakamoto

Tatsuo Nagata

Isao Kondo

Toshiro Ohmura

Kouichi Ishibashi

Tetsuo Mitsuhashi

Mitsuo Konno

A decoder apparatus which includes a de-multiplexer, which is configured to divide motion picture data from a transport stream, a video decoder, which is configured to decode the divided motion picture data, and a first re-formatter on-screen unit, which is configured to display motion picture data and at least one of first and second graphic data on a screen. The first re-formatter on-screen unit converts motion picture data of a first aspect ratio, which is decoded by the video decoder, and first graphics data, which is produced by applying information relating to a caption corresponding to the motion picture data, into a second aspect ratio, when outputting the motion picture data of the first aspect ratio after conversion into the second aspect ratio, without converting the aspect ratio of second graphic data, which is produced by applying information relating to a program guide.

Decoder device and receiver using the same

A receiver includes a motion picture data decoder which decodes motion picture data to obtain decoded motion picture data, a memory which stores the decoded motion picture data, a video processing unit which mixes the decoded motion picture data with first graphics data and converts the motion picture data to obtain first on-screen data mixed and first format-converted motion picture data, and a second on-screen data multiplexer which mixes the decoded motion picture data with second graphics data to obtain second on-screen data-mixed motion picture data. A first output device outputs the first on-screen data mixed and first format-converted motion picture data, a second output device outputs the second on-screen data mixed motion picture data.

Receiver having motion picture data decoder

An object of the present application is to provide the display of motion picture data used in both of analog and digital broadcasts with high picture quality and a common user interface. The above object can be achieved by providing a plurality of picture format converters, a plurality of OSD circuits, and means for storing motion picture data used in an analog broadcast in a common memory.

A boundary position detection apparatus in which the position of an imageless part (containing no meaningful image information) lying at the upper part or/and the lower part of a picture is precisely detected from a video signal. A line decision circuit decides whether each of lines constituting the picture belongs to an image part (containing meaningful image information) or to the imageless part. A boundary decision circuit decides the boundary between the image part and the imageless part. A time integration circuit integrates the detected boundary positions temporally, and determines a final boundary position. A detection control circuit finds an image-part region from the final position, detects the average luminance of the region and controls the integrating time interval of the time integration circuit with the average luminance.

Apparatus for detecting position of featuring region of picture, such as subtitle or imageless part

An object of the present application is to provide the display of motion picture data used in both of analog and digital broadcasts with high picture quality and a common user interface. The above object can be achieved by providing a plurality of picture format converting means, a plurality of OSD means and means for taking motion picture data used in an analog broadcast in a common memory.

Apparatus for detecting position of featuring region of picture, such as

To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal. A clock generating circuit supplies the field memory with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit reads a video signal from the field memory with a line period corresponding to a magnification factor and inhibits writing to a one-line memory with the same period to provide a line delayed output for an output signal from the field memory. A vertical interpolating circuit generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit.

Television receiver capable of enlarging and compressing image

A wide television receiver which converts a video input signal having an aspect ratio 4:3 or 16:9 into a display format permitting selecting of display with horizontal compression, without horizontal compression, with vertical magnification, or without vertical magnification to present the display on a wide display having an aspect ratio 16:9.

Signal processor for a wide televison receiver

There is disclosed a compatible television receiver capable of receiving and reproducing both the standard system television signal and the high definition television signal and capable of confining the degradation of picture quality of the high definition television signal to the minimum, in which the received standard system television signal and high definition television signal are respectively converted to non-interlace signals, and scanning is selectively performed with either of non-interlace video signals to display images. The television receiver according to the present invention comprises a first conversion circuit for receiving an interlace standard system television signal and converting it into a non-interlace television signal, a second conversion circuit for receiving an interlace high definition television signal and converting it into a non-interlace televison signal, a circuit for discriminating whether the received signal is the standard system television signal or the high definition signal, and a circuit for selecting either of outputs of the first and second conversion circuits on the basis of the result obtained in the discrimination circuit.

Television receiver compatible with both standard system television

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Yokohama, Japan

Shinobu Torikoshi