Mitsubishi Denki Kabushiki Kaisha

Shinobu Takahama

Satoshi Hirakawa

Akinobu Tamaki

Toshikazu Masumoto

Kunitaka Kamishima

Hitoshi Yamano

Teruki Hyougatani

Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.

Method of fabricating power semiconductor device and lead frame

In order to maintain parasitic inductances of main electrodes at low levels also during operation of a semiconductor device, upright portions of main electrode plates serving as paths of main currents are sealed in a side wall portion of a resin case, whereby the main electrode plates are fixed to the case while being maintained in parallel with each other. Further, lower end portions are opposed in parallel with each other through a flat insulating spacer. Thus, parasitic inductances caused in the main electrode plates are suppressed. Further, the lower end portions are not fixed to a circuit board but electrically connected to a power transistor through wires. Therefore, no deformation of the main electrodes is brought by thermal deformation of the circuit board following heat generation of the transistor, whereby the parallelism of the main electrode plates is maintained also during the operation of the device. Consequently, the parasitic inductances are maintained at low levels also during operation of the device.

Semiconductor device having electrodes embedded in an insulating case

There is disclosed a semiconductor device wherein electrode terminals (2), elements (6) and wires (7) are disposed on a base plate (5) of a case (4) filled with only epoxy resin (1). The epoxy resin (1) contains impurities such as halogen and alkaline metallic salts in an amount of not more than 5 ppm and has a linear expansion coefficient of 5.times.10.sup.-6 to 25.times.10.sup.-6 when hardened. The semiconductor device provides for direct sealing of the components, whereby its size and cost are reduced.

Semiconductor device and resin for sealing a semiconductor device

A semiconductor device where electrode terminals (2), elements (6) and wires (7) are disposed on a base plate (5) of a case (4) filled with only epoxy resin (1). The epoxy resin (1) contains impurities such as halogen and alkaline metallic salts in an amount of not more than 5 ppm and has a linear expansion coefficient of 5.times.10.sup.-6 to 25.times.10.sup.-6 when hardened. The semiconductor device provides for direct sealing of the components, its size and cost are therefore reduced.

Semiconductor device, resin for sealing same and method of fabricating

In manufacturing an insulation substrate used in a semiconductor device, a metal plate (10) having relatively thick body portions (11a,11b,11c) and relatively thin linkage portions (12,13) is prepared. The body portions are spaced from each other and the linkage portions link up the respective body portions. The metal plate is fixed to a metal flat plate (1) through a resin layer (2). The linkage portions are then removed through selective etching. The structure thus obtained is cut into a plurality of unit structures, to thereby obtain an in insulation substrate having conductive circuit patterns thereon.

Method of manufacturing insulation substrate for semiconductor device

In manufacturing an insulation substrate used in a semiconductor device, a metal plate (10) having relatively thick body portions (11a, 11b, 11c) and relatively thin linkage portions (12,13) is prepared. The body portions are spaced from each other and the linkage portions link up the respective body portions. The metal plate is fixed to a metal flat plate (1) through a resin layer (2). The linkage portions are then removed through selective etching. The structure thus obtained is cut into a plurality of unit structures, to thereby obtain an in insulation substrate having conductive circuit patterns thereon.

A semiconductor device is provided within an outer container (21) made of a ceramic which is of a box shape having an opening in an upper portion thereof and a bottom plate and also having a stepped portion (21a) at the position in an intermediate height of an inner wall of side plates. A metalized layer (22) is deposited in inner and outer surfaces of the bottom plate and a surface of the stepped portion. A metal plate (30) is brazed by a silver solder (26) on the metalized layer of the outer surface of the bottom plate and at the same time, a common metal substrate (27) is also brazed by a silver solder (26) on the metalized layer (22) on the inner surface of the bottom plate. A plurality of external electrodes (23, 23', 24, 25) in a frame shape of a conductor plate are connected to the metalized layer (22) of the surface of the stepped portion (21a) by a silver solder (26). A heat sink plate (10 ) is connected to the common metal substrate (27) by means of soldering (6) and a semiconductor chip (7, 28) is soldered on the heat sink plate (10). After a semiconductor chip (7, 28) is electrically connected to the plurality of electrodes (23, 23', 24, 25) and the metal plate (30), the container (21) is filled with a soft resin (12) for sealing.

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Fukuoka, Japan

Shinobu Takahama