Sony Corporation

Shinobu Nakamura

Mamoru Kudo

Jun Yamane

Hirofumi Shimizu

Satoru Ooshima

Kazutoshi Shimizume

Mamoru Akita

Nobuyuki Asai

In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Phase error determination method and digital phase-locked loop system

In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Digital PLL device

In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a CD reproduced signal or a DVD reproduced signal, for example. Although the frequency of the channel clock in synchronism with the reproduced signal differs in different signal formats, the above configuration makes it possible to reproduce the channel clock properly in accordance with a plurality of signal formats only by the operation of changing the frequency dividing ratio in a PLL circuit.

Phase-locked loop circuit for reproducing a channel clock

A disc reproduction device, in which at the time of normal reproduction, a rotational speed of a spindle is detected based on a reproduction signal from the disc by a rotational speed counting circuit, a control signal that makes a speed error with respect to a reference speed zero is given to a first VCO as the control voltage thereof, a reproduction clock is generated while controlling the frequency and phase at a digital PLL circuit by using the oscillation output thereof as the reference frequency of the first PLL circuit containing a second VCO and in which, at the time of access, the control signal to the first VCO is switched to the output signal of the phase comparator by the switch circuit under the control of the controller and a multiple PLL circuit containing the first VCO, phase comparator, LPF, and so forth, is constituted to make the oscillation frequency of the first VCO track the reproduction speed at the destination of access predicted based on the access information by the controller. As a result, the access time can be reduced.

Disc player reproduction circuit with reproduction speed dependent VFO

A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a means of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Disc player apparatus having a disc rotational speed controller

A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a device of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Disc player apparatus having a signal processing circuit which produces

An optical disc player wherein an amount of jitter in a write clock as opposed to a read clock is detected by a jitter counter, a the write clock is counted by a reference counter for the number of frames, the jitter amount is added/subtracted to/from the count output by an adder/subtractor, an offset for the predetermined number of frames is given to a result of the addition/subtraction to generate a subcode synchronizing signal completely synchronized with the read clock. The subcode synchronizing signal is outputted through an output determining circuit only when a reproduction subcode synchronizing signal is found matching by a match detector with the count output of the reference counter twice successively. The device can correctly perform sound linking even for software having successive fixed patterns and perform sound linking without error even if reproduction data at sound linking point is processed with previous-value hold or interpolation.

Optical disc player with shockproof controller and method of processing

A modulator suppressing a low-frequency component of a recording waveform while limiting maximum and minimum recording wavelengths, comprising a margin bit generating circuit for generating a most suitable margin bit pattern based on a signal concerning a final recording waveform level of each of n channel bit patterns to be put before a margin bit pattern to be inhibited, control signals concerning a polarity of a cumulative digital sum variation, a control signal coming from a digital sum variation integrating circuit to switch between gains by detecting a magnitude of an absolute value of the digital sum variation, and a signal concerning the cumulative digital sum variation of each of the n channel bit patterns to be put after the above-mentioned margin bit pattern.

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Kanagawa, Japan

Shinobu Nakamura