Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Leland Stanford Junior University

Kioxia Corporation

Toshiba America Research, Inc.

Shinobu Fujita

Hiroki Noguchi

Keiko Abe

Tetsufumi Tanamoto

Kazutaka Ikegami

Shinichi Yasuda

Kumiko Nomura

Satoshi Takaya

Susumu Takeda

Tomoaki Inokuchi

Hiroaki Yoda

Katsuhiko Koui

Naoharu Shimomura

Masato Oda

Mari Matsumoto

Ryuji Ohba

Hideyuki Sugiyama

Yuichi Ohsawa

Atsuhiro Kinoshita

Takao Marukame

Chika Tanaka

Yuuzo Kamiguchi

Tetsuro Iwamura

Yoshiaki Saito

Satoshi Saito

Satoshi Shirotori

Thomas H Lee

Kosuke Tatsumura

Koichiro Inomata

Kiwamu Sakuma

Koichi Muraoka

Yuichiro Mitani

Koichi Fujisaki

Yoshifumi Nishi

Mizue Ishikawa

Daisuke Saida

Ken Uchida

Yushi Kato

Takahiro Kurita

Junji Koga

Takao Noda

Daisuke Hagishima

Atsushi Kurobe

Yasuo Ashizawa

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.

Arithmetic device having magnetoresistive effect elements

A magnetic device includes: a first conductive layer; a first magnetoresistive effect element disposed on the first conductive layer and including a first control terminal; and a first circuit configured to supply a first current in a first direction into the first conductive layer and apply a first control voltage to the first control terminal of the first magnetoresistive effect element, wherein in a case in which the first current is supplied to the first conductive layer, the first magnetoresistive effect element holds a value corresponding to a logical disjunction between a first value of first data in the first magnetoresistive effect element and a second value of the first control voltage corresponding to second data.

Magnetic device storing first and second values

A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.

Memory system and processor system

According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.

Magnetic memory device

According to one embodiment, a magnetic memory device includes a first conductive layer, a first stacked body, and a controller. The first conductive layer includes a first region, a second region, and a third region between the first region and the second region. The first stacked body includes a first magnetic layer, a second magnetic layer provided between the third region and the first magnetic layer in a first direction crossing a second direction, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second direction is from the first region toward the second region. The controller electrically is connected to the first region, the second region, and the first magnetic layer. The controller performs at least first to third operations. In the operations, the controller sets the first stacked body to first to third resistance state.

According to one embodiment, a magnetic memory includes: a memory area; a first memory unit disposed in the memory area and including h first magnetoresistive effect elements arrayed on a first conductive layer; and a first circuit configured to receive i-bit first data, convert the first data into j-bit (j=h) second data, and write the second data in the first memory unit. The second data includes m first values and (j&#x2212;m) second values, and m and j have a relationship given by 'j/2&#x2212;1&#x2264;m&#x2264;j/2+1'.

Magnetic memory including meomory units and circuits for reading and writing data and memory system

A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.

Cache memory and processor system

A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.

Controlling write pulse width to non-volatile memory based on free space of a storage

A memory control circuitry has a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor, a write controller to write data in the write destination selected by the write destination selector, and an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other. When there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register.

Memory control circuitry, memory system and processor system

A memory system has a first memory to store first-granularity data having a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.

Memory system having multiple different type memories with various data granularities

A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

Memory system having nonvolatile memory and volatile memory and processor system

A memory system has a first memory which comprises a nonvolatile memory data region, and a second memory which stores data before storing in a third memory, the data not being written back on the third memory in a lower-level with access priority lower than access priority of the first memory, among data inside the nonvolatile memory data region, wherein the second memory has a bit error rate lower than a bit error rate of the first memory.

Memory system

A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. The error corrector to correct an error included in data read from the non-volatile memory. The error information storage, based on an error rate when a predetermined number or more of data is written in the non-volatile memory and read therefrom, to store first information on whether there is an error in the written data, on whether there is an error correctable by the error corrector in the written data, and on whether there is an error uncorrectable by the error corrector in the written data. The access controller, based on the first information, to control at least one of reading from or writing to the non-volatile memory.

According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

Magnetic memory and memory system

Growing community of inventors

Tokyo, Japan

Shinobu Fujita