Sony Corporation

Sony Semiconductor Solutions Corporation

Shinjiro Kameda

Keiji Mabuchi

Tsutomu Haruta

Eiji Makino

Tetsuo Nomoto

Eiichi Funatsu

A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.

Solid state imaging device having variation in optical black pixel structures relative to image generating pixel structures to provide substantially equivalent dark current

A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example &#x2212;1V).

Solid state imaging device and camera system

An MOS type solid state imaging device in which unit pixelseach having a photodiode, a transfer transistorfor transferring the signal of the photodiodeto a floating node N, an amplifier transistorfor outputting the signal of the floating node Nto a vertical signal line, and a reset transistorfor resetting the floating node Nare arrayed in a matrix and in which a gate voltage of the reset transistoris controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example &#x2212;1V).

A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example &#x2212;1V).

Solid-state imaging device

There is provided a solid-state imaging device including: a plurality of aperture pixels configured to be used for capturing of an image; a plurality of first light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the first light-shielded pixels being larger than a temperature dependence of a dark current in the aperture pixels; and a plurality of second light-shielded pixels configured to be shielded from light for detection of an optical black level, a temperature dependence of a dark current in the second light-shielded pixels being smaller than a temperature dependence of a dark current in the aperture pixels.

Solid state image pickup device having optical black pixels with temperature characteristics above and below temperature characteristics of aperture pixels

A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixelseach having a photodiode, a transfer transistorfor transferring the signal of the photodiodeto a floating node N, an amplifier transistorfor outputting the signal of the floating node Nto a vertical signal line, and a reset transistorfor resetting the floating node Nare arrayed in a matrix and in which a gate voltage of the reset transistoris controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example &#x2212;1V).

Growing community of inventors

Kanagawa, Japan

Shinjiro Kameda