Renesas Electronics Corporation

Shinji Yamano

Shinichi Asano

Osamu Nakamura

When graphics computations are to be performed to calculate the display data of a figure to be drawn within a frame that is formed of a plurality of lines in accordance with input vector data, the present invention reduces the storage capacity of a RAM to which a work area for storing intermediate data is allocated. When the graphics computations are to be performed, the frame in which the figure is to be displayed is segmented into a plurality of drawing areas for each of the lines. As regards the work area for storing the intermediate data, the same work area is allocated to all the drawing areas. The graphics computations for calculating the intermediate data of the individual drawing areas are sequentially performed by repeatedly using the same work area.

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Tokyo, Japan

Shinji Yamano