Fujitsu Corporation

Fujitsu Semiconductor Limited

Shinji Wakasa

Yasuyuki Mitsumori

Tomoyuki Yamaguchi

Susumu Tominaga

A digital delay locked loop circuit generates a delay value to delay the timing of taking in read-data by a memory interface when data is read from a memory. The digital delay locked loop circuit includes a selector that selects either one of a clock signal and a data strobe signal as a signal to output; a delay line that induces delay on the signal output from the selector when the signal passes through the delay line; and a phase-comparing/delay-value determining unit that compares a phase of the clock signal and a phase of the signal output from the delay line, and that determines a delay value that defines an amount of delay to be induced on the data strobe signal when passing through the delay line.

Digital DLL circuit

A JPEG image processing circuit, capable of performing a JPEG process at high speed, and with low power consumption, and of automatically recovering from a slight trouble, has been disclosed. In the JPEG processing circuit, a JPEG processing section is configured so as to comprise a plurality of JPEG processing cores and a plurality of data storage regions provided in correspondence with the plurality of JPEG processing cores, and when each of the JPEG processing cores performs the process in parallel, the unprocessed data required for the process of each of the JPEG processing cores is stored in each of the data storage regions, corresponding to each of the JPEG processing cores, via a common bus connected to an image memory.

JPEG image processing circuit

A transmission base flow control device including a first credit counter, shared by an active system and a preparatory system of a reception device, managing a credit value of the active system; a second credit counter and a third credit counter counting the credit values for each system of the active system and the preparatory system of the reception device; a differential counter holding a difference between the credit value counted by the second credit counter and the credit value counted by the third credit counter; and a control unit matching, according to the difference held by the differential counter, the credit values of the first credit counter and the second credit counter or the credit values of the first credit counter and the third credit counter with a credit value corresponding to the reception device of a new active system after switching the system of the reception device.

Transmission base flow control device

A plurality of modules, each connected to communication lines, are interconnected by a logically separated interprocessor communication bus for transferring header information and control information and a frame transfer bus for transferring data. When each module receives data from a line, the module generates a header containing header information from the received data, stores the header and user data in respective queue-type data storage sections, and transmits the header on the interprocessor communication bus; when one of the other modules detects its own identification from the header on the bus, the module sends a data send request to the transmitting module which in response reads the data from the data storage and outputs it on the frame transfer bus for transmission to the requesting module.

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Kawasaki, Japan

Shinji Wakasa