Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Microcomputer Engineering, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Hitachi Vsli Engineering Corp.

Shinji Udo

Kazuyoshi Oshima

Kazuhiko Kajigaya

Yasuhiro Kasama

Hiroshi Yoshioka

Makoto Morino

Mitsuhiro Takano

Sinichi Miyatake

Manabu Tsunozaki

Masashi Horiguchi

Akira Endo

Ryoichi Hori

Takashi Yamazaki

Kazuyuki Miyazawa

Jun Etoh

Yuji Sakai

Yasunori Yamaguchi

Tetsurou Matsumoto

Shinichi Ikenaga

Eiji Miyamoto

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Hiroaki Kotani

Kyoko Ishii

Akihiko Hoshida

Tsutomu Takahashi

Shinichi Miyatake

Michitaro Kanamitsu

Yoshihisa Koyama

Hidetomo Aoyagi

Kiichi Manita

Masanori Tazunoki

Koichi Nozaki

Masahiro Sakai

Hiyori Koyama

Kazuaki Ujiie

Kazue Kikuchi

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Nonvolatile memory device

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor memory device having zigzag bonding pad arrangement

Growing community of inventors

Akishima, Japan

Shinji Udo