Renesas Electronics Corporation

Ricoh Company, Ltd.

Sony Corporation

Toyo Seikan Kaisha, Ltd.

Asano Laboratories Co., Ltd.

Murata Manufacturing Co., Ltd.

Minebea Company, Limited

Toyo Seikan Group Holdings, Ltd.

Toyo Aerosol Industry Co., Ltd.

Shinji Tanaka

Makoto Yabuuchi

Yuta Yoshida

Kenichi Kawase

Takakazu Hirose

Noriaki Maeda

Ken Shibata

Toshiaki Sano

Kikuo Matsuoka

Takashi Fujinaga

Akira Takamuku

Koji Nii

Atsushi Kikuchi

Yuichiro Ishii

Yoshikazu Saito

Kazumasa Nomoto

Ichiro Fujiwara

Toshihiro Takai

Hiroshi Aozasa

Kenichi Mizoguchi

Hideki Usami

Yasuyo Sano

Tomoaki Haruta

Atsushi Suzuki

Hideki Kimura

Toshihiko Suzuki

Yasuo Katano

Takahiro Sakaguchi

Takayuki Ishihara

Shigetaka Tomiya

Shuji Goto

Hisakazu Yasumuro

Toyotaka Kataoka

Minoru Morikawa

Kazuhiko Tokunaga

Hideaki Kobayashi

Kiyokazu Yamada

Manabu Nishimura

Akihide Kashiwagi

Kengo Matsumoto

Jun Matsushima

Atsushi Fukahori

Takuo Shibata

Kouji Kuriyama

Keiji Fukue

Madoka Yamaguchi

Machiko Sugiyama

Hiroaki Gotou

Keiji Kobayashi

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Semiconductor device

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Semiconductor storage device

Disclosed is a multilayered container having an intermediate layer comprising an oxygen-absorbable barrier resin composition showing excellent processability upon molding. Specifically disclosed is a multilayered container which comprises an inner layer and an outer layer each comprising an olefin resin and an intermediate layer provided between the inner layer and the outer layer and comprising an oxygen-absorbable barrier resin composition, wherein the oxygen-absorbable barrier resin composition has a cooling crystallization peak temperature lower than that of a base resin (an oxygen barrier resin) which constitutes the oxygen-absorbable barrier resin composition, the multilayered container is formed by a solid-phase-forming process at a temperature lower by 1 to 15&#xb0; C. than the cooling crystallization starting temperature (Tc2) of the base resin, and the body of the container shows a calorific value of less than 0.5 J/g by the isothermal crystallization after heating from 30&#xb0; C. to 130&#xb0; C. at a heating rate of 100&#xb0; C./min in a thermal analysis of the body.

Multilayered container

A protection circuit is provided with: a suppression element that is coupled to a power source side of a main circuit and suppresses current flowing into the main circuit that drives a load; and a soft start circuit that is configured to gradually increase voltage of a control terminal of the suppression element when voltage is applied to the soft start circuit from a boosting circuit used for controlling the main circuit.

Protection circuit and control circuit

A rechargeable battery including: a positive electrode; a negative electrode including active material; and an electrolytic solution, in which the active material is capable of occluding and releasing lithium ions and includes Si and O as constituent elements, and an atomic ratio (Si/(Si+O)) of Si with respect to Si and O is 30 atomic % to 75 atomic % in a surface of the active material.

Active material for rechargeable battery, rechargeable battery, and electronic apparatus

An internal pouch held in a double-structured aerosol can, composed of first and second internal pouches for containing first and second agents, respectively, the aerosol can being capable of simultaneously ejecting the first and second agents. The first internal pouch has a layer constitution that includes a polyolefin inner layer, an adhesive resin layer on the inner layer side, an aluminum foil, an adhesive resin layer on the outer layer side and a thermoplastic resin outer layer; the second internal pouch has a layer constitution that includes a polyolefin inner layer, an adhesive resin layer on the inner layer side, an aluminum foil, an adhesive resin layer on the outer layer side and a thermoplastic resin outer layer; and the adhesive resin forming the adhesive resin layer on the inner layer side of the first internal pouch contains a polyether type urethane resin.

Internal pouch held in a double-structured aerosol can

A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor deviceincludes a write word line WLA and a read word line WLB each coupled to memory cells. A read operation activates the read word line WLB corresponding to the selected memory cell. A write operation activates the write word line WLA corresponding to the selected memory cell. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Semiconductor device having timing control for read-write memory access operations

Growing community of inventors

Kanagawa, Japan

Shinji Tanaka