Renesas Electronics Corporation

Hitachi, Ltd.

Nec Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ihi Corporation

Tosoh Corporation

Mitsubishi Electric Corporation

Nippon Telegraph and Telephone Corporation

Kawasaki Jukogyo Kabushiki Kaisha

Hitachi Construction Machinery Co., Ltd.

National Institute for Materials Science

Hitachi Koki Co., Ltd.

Japan Tobacco Inc.

Ricoh Company, Ltd.

Shinji Tanaka

Kazuo Sato

Makoto Yabuuchi

Yoshio Kawamura

Keiji Saito

Osamu Iwamoto

Katsuyoshi Nakajima

Nobuya Kurikawa

Momoko Ogitani

Natsumi Nishihama

Wataru Saitoh

Kazumasa Aoki

Yasuyuki Ogawa

Toru Taniguchi

Satoshi Shibuya

Kaori Ito

Eriko Kioi

Tsuyoshi Mikkaichi

Yuichiro Ishii

Toshiaki Sano

Katsuyoshi Takahashi

Hiroyuki Kohida

Jun Hosoi

Hideo Miura

Masaki Tsukude

Hiroyuki Ohta

Hiroshi Inoue

Yoshikazu Saito

Masatoshi Kanamaru

Nobuyuki Suzuki

Hideyuki Aoki

Naoto Ban

Akihiko Ariga

Atsushi Hosogane

Shunya Nagata

Junya Kishi

Yasuo Okutomi

Takatoshi Shimizu

Masatoshi Sakurano

Masamichi Mizoguchi

Tsuneo Terasawa

Keiichiro Oishi

Shigeo Ohashi

Yoshishige Endo

Hiroshi Kanda

Toshio Hatada

Isao Ishikawa

Kiyotada Funane

Kuninori Imai

Takeji Shiokawa

Shigeo Kato

Morio Tamura

Toshihiro Inayama

Ryuji Kono

Akiko Yamamoto

Hisayoshi Hashimoto

Kazuyoshi Hatano

Yuta Yanagitani

Harumasa Onozato

Kiyoshi Tanaka

Fujio Sato

Yuichiro Nakai

Koji Tanaka

Mikio Asakura

Yasuyuki Saito

Hiroyuki Mano

Kenji Kondo

Seiji Sawada

Yukio Honda

Noriaki Maeda

Yasuhiko Tsukikawa

Kiyoshige Kinugawa

Takeshi Harada

Takeo Miki

Kenichi Yasuda

Kenko Uchida

Ken Shibata

Yuji Yoshitomi

Noriyuki Ashiwake

Masao Morimoto

Susumu Tanida

Tsuguji Tachiuchi

Takeshi Araya

Yoshisato Yokoyama

Yasuhiro Matsumoto

Hiroyuki Tsuruoka

Nobuyuki Ohkawa

Yohei Sawada

Tsuyoshi Soneda

Takamitsu Nakazaki

Isao Endo

Manabu Nishimura

Takaharu Matsui

Takahiko Fukiage

Akihiro Ueda

Nagayoshi Hiromitsu

Eiichi Harada

Reiko Inoue

Yoshihisa Hosoe

Yoshu Yoshiba

A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.

Semiconductor device

A semiconductor device includes a memory array having a plurality of associative memory cells arranged in a matrix form for storing entries. The memory array is divided into a plurality of memory blocks for sequentially performing a retrieval operation along a column direction, and further includes a plurality of match lines corresponding to the respective memory blocks and provided correspondingly to each memory cell row, a plurality of search lines corresponding to the respective memory blocks and provided correspondingly to each memory cell column, and a plurality of match amplifiers corresponding to the respective memory blocks and provided to the plurality of match lines. The match line provided correspondingly to the preceding memory block is set to become shorter than the match line provided correspondingly to the subsequent memory block. The memory array further includes a timing control unit for controlling timing for driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.

Semiconductor device and semiconductor system

An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R: e.g., a C1-C6 alkyl group; R: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R: e.g., a C1-C6 alkyl group.

Griseofulvin compound

The present invention provides a surface treatment method that improves antimicrobial activity of copper or a copper alloy and enhances immediate effects of antimicrobial actions on the surface of the copper or the copper alloy. A surface treatment method for copper or a copper alloy according to the present invention comprises preparing a reducing agent solution containing a biological reducing substance, and treating the surface of the copper or the copper alloy with the reducing agent solution. The present invention also provides a surface treatment liquid for sterilizing copper or a copper alloy, in which the surface treatment liquid contains a biological reducing substance. The present invention also provides a sterilization method that comprises bringing copper or a copper alloy treated by the surface treatment method into contact with a surface of an object to sterilize the surface of the object.

Surface treatment method for copper or copper alloy, surface treatment liquid for sterilizing copper or copper alloy, and sterilization method using copper or copper alloy treated by said method

An object of the present invention is to provide a compound that has a specific chemical structure having an activation effect on SIRT6 and is useful as an active component for preventing and treating inflammatory diseases, and the present invention relates to a compound represented by Formula (1) or a pharmaceutically acceptable salt thereof,

Urea compound having substituent

An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below:R: e.g., a C1-C6 alkyl group; R: a C1-C6 alkyl group;A: e.g., an oxygen atom; and R: e.g., a C1-C6 alkyl group.

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.

A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

An aft section structure of a jet engine with an axis is comprised of a casing defining a duct around the axis and opened axially fore and aft; a cone tapering aftward at a first angle with the axis and having a pointed end; guide vanes, each of the vanes radially extending from the cone to the casing and comprising a pressure side at a second angle with a plane containing the axis; spray bars, each of the spray bars extending radially within the duct and comprising trailing sides, each of the trailing sides being directed aftward at a third angle with a plane containing the axis; and flame holders, each of the flame holders extending radially within the duct and comprising one or more interior sides, each of the interior sides being directed aftward at a fourth angle with a plane containing the axis.

Engine aft section structure

An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

Content addressable memory

Growing community of inventors

Tokyo, Japan

Shinji Tanaka