Fujitsu Corporation

Shinji Sugatani

Yoshihiro Takao

Daisuke Matsunaga

Hikaru Kokura

Takayuki Wada

Koichi Sugiyama

Tohru Fujita

Satoshi Sekino

Hiroyuki Ohta

Koichi Hashimoto

Kazuhiko Takada

Satoshi Nakai

Ryota Nanjo

Yasuhiro Sambonsugi

Yoichi Morriyama

Hiroyuki Naganuma

The semiconductor device comprises a semiconductor substratewith a trenchand a trenchformed in; a device isolation filmburied in the trenchand including a liner film including a silicon nitride filmand an insulating filmof a silicon oxide-based insulating material; a device isolation filmburied in the bottom of the trench; and a capacitor formed on a side wall of an upper part of the second trenchand including an impurity diffused regionas a first electrode, a capacitor dielectric filmof a silicon oxide-based insulating film and a second electrode

Semiconductor device with shallow trench isolation which controls mechanical stresses

There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Semiconductor device and method of manufacturing the same

A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis of the device formation layer be shifted from a corresponding direction of a crystallographic axis of the supporting substrate. Semiconductor devices are formed in the device formation layer within a plurality of areas divided by scribe lines extending to a direction being parallel to a direction of a crystallographic axis where the supporting substrate is easy to be cleaved. The laminated substrate is split into a plurality of chips by cleaving the supporting substrate along the scribe lines. A semiconductor device can easily be split into chips even if a moving direction of carrier and an extending direction of wiring are shifted from an easy-cleaved direction of a crystallographic axis.

Manufacturing method of semiconductor device and semiconductor chip using SOI substrate, facilitating cleaving

First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.

Semiconductor device and its manufacture method

A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second impurity diffusion regions of a second conductivity type on both sides of the gate electrode. A high leak current structure is formed which makes a leak current density when a reverse bias voltage is applied across the first impurity diffusion region and first well become higher than a leak current density when the same reverse bias voltage is applied across the second impurity diffusion region and first well.

Semiconductor device using junction leak current

There are provided the steps of forming a tunnel insulating film on a semiconductor substrate, forming a first semiconductor film constituting a lower portion of a floating gate on the tunnel insulating film, forming device isolation recesses by etching device isolation regions on the first semiconductor film, the tunnel insulating film, and the semiconductor substrate, forming an device isolation insulating film in the device isolation recesses and on the first semiconductor film, removing the device isolation insulating film from an upper surface of the first semiconductor film and thinning the device isolation insulating film on the device isolation recesses, growing selectively a second semiconductor film serving as an upper portion of the floating gate on the first semiconductor film and growing the second semiconductor film on the device isolation insulating film to extend in the lateral direction, forming a dielectric film on the floating gate, and forming a conductive film serving as a control gate on the dielectric film.

Semiconductor device and semiconductor chip using SOI substrate

The method for fabricating a semiconductor device comprises an insulation film forming step of forming an insulation film,on a semiconductor substrate,, a semiconductor layer forming step of forming a semiconductor layer,on the insulation film,, and an impurity implanting step of implanting an impurity containing hydrogen into the semiconductor layer,, the method being characterized by further comprising a fluorine implanting step of implanting fluorine in at least the insulation film,. The dangling bonds of the insulation film can be bonded with the fluorine, whereby the fluorine, which has higher bonding energy with respect to silicon of the insulation film than hydrogen, is never dissociated from the silicon of the insulation film in the following heat treatments, BT stress test, etc. Accordingly, an interface state density in the interface between the insulation film and the semiconductor substrate can be depressed low, and a fixed charge in the insulation film can be depressed small. The semiconductor device and the method for fabricating the same can be reliable. The fluorine ion dose is suitably set to thereby prevent the insulation film from thickening. The method for fabricating a semiconductor device having good electric characteristics can be provided.

Semiconductor device and method for fabricating the same

A structure of high packing density EPROM having floating gate type FET memory cells and a fabrication process thereof are disclosed. Marginal spaces for mask alignment and bird's beak in prior art EPROM device have been cut down by applying a self alignment technique to determine both the gate length and gate width. The process for fabricating the device is disclosed. On a substrate first gate insulation film and first conductive polysilicon layer are formed. Parallel grooves for device separation are formed in a direction of gate length by photolithography. The space between the groove defines the gate width, and the width of the groove determines the spacing between the cell FETs. The groove is buried by SiO.sub.2 deposited chemical vapor deposition. The surface is etched to expose the first polysilicon layer. On this surface, a second gate insulation film and second conductive polysilicon layer are formed. The substrate is then etched leaving a parallel stripes orthogonal to the device separation grooves. The spacing of the stripe determines the device separation in the direction of gate length. Utilizing this stripes as a mask, the substrate is etched off to expose the substrate. To the exposed substrate are doped to form sources and drains. Applying the inventive process, the packing density of the memory cell has been increased by 30%.

Growing community of inventors

Kawasaki, Japan

Shinji Sugatani