Matsushita Electric Industrial Co., Ltd.

Arakawa Chemical Industries, Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Shinji Ozaki

Hideki Goda

Kazufumi Ogawa

Mamoru Soga

Naoki Sasagawa

Katsuhiko Ikeyatsu

Hiroaki Yamamoto

Yoshito Nishimichi

Katsuya Okubo

Satoru Aoyama

Satoshi Ogura

Norihisa Mino

Masaitsu Nakajima

Shigeo Ikuta

Takao Yamamoto

Nobuo Higaki

Masato Suzuki

Hiroyuki Morishita

Akira Miyoshi

Akihiko Ohtani

Toru Morikawa

Toshio Sugimura

Taizou Tsujimoto

Yoshiaki Kasuga

Seiji Tokunoh

Keisuke Kaneko

Masahide Kakeda

Tomohisa Sezaki

Toshinobu Nakao

Provided are a binder aqueous solution for a lithium ion battery, a negative electrode slurry for a lithium ion battery, a negative electrode for a lithium ion battery, and a lithium ion battery. The binder aqueous solution for a lithium ion battery has a pH of 5 or higher and contains: a water-soluble polymer (A) that is a polymer of a monomer group containing, with respect to 100 mol % of the monomer group, 15 mol % to 99.9 mol % of an unsaturated carboxylic acid or an inorganic salt thereof, and that has a glass transition temperature of 110° C. or lower; and a hydrolyzed partial condensate (B) of an amino group-containing trialkoxysilane.

Binder aqueous solution for lithium ion battery, slurry for negative electrode of lithium ion battery, negative electrode for lithium ion battery, and lithium ion battery

Provided are a binder aqueous solution for a lithium-ion battery, a slurry for a lithium-ion battery negative electrode, a negative electrode for a lithium-ion battery, and a lithium-ion battery. The binder aqueous solution for a lithium-ion battery contains a water-soluble poly(meth)acrylamide (A). The water-soluble poly(meth)acrylamide (A) is a polymer of a monomer group containing, with respect to 100 mol % of the monomer group, 30 mol % to 95 mol % of a (meth)acrylamide group-containing compound (a), and 5 mol % to 40 mol % of an alkoxyalkyl (meth)acrylate (b) represented by the following general formula (1),CH&#x2550;C(R)&#x2014;CO&#x2014;O&#x2014;R&#x2014;O&#x2014;R&#x2003;&#x2003;(1) (in which Ris a hydrogen atom or a methyl group, Ris an alkylene group having 1 to 4 carbon atoms, Ris an alkyl group having 1 to 4 carbon atoms, and a total number of carbon atoms of the groups R, Rand Ris 5 or less.)

Binder aqueous solution including copolymer of (meth)acrylamide and alkoxyalkyl (meth)acrylate, slurry including the same, negative electrode, and lithium-ion battery

To provide a conductive carbon material dispersing agent for a lithium ion battery, a slurry for a lithium ion battery electrode, an electrode for a lithium ion battery, and a lithium ion battery The disclosure provides a conductive carbon material dispersing agent for a lithium ion battery including a water-soluble poly(meth)acrylamide (A-1) which contains 2 to 60 mol % of structural units derived from a (meth)acrylamide group-containing compound (a) and 10 to 70 mol % of structural units derived from an unsaturated sulfonic acid or salts thereof (b), and which has a weight average molecular weight of 10,000 to 300,000.

Conductive carbon material dispersing agent for lithium ion battery, slurry for lithium ion battery electrode, electrode for lithium ion battery, and lithium ion battery

Provided are a thermally crosslinkable binder aqueous solution for a lithium-ion battery, a thermally crosslinkable slurry for a lithium-ion battery negative electrode, a negative electrode for a lithium-ion battery, and a lithium-ion battery. The thermally crosslinkable binder aqueous solution for a lithium-ion battery contains a water-soluble poly(meth)acrylamide (A) and a divalent or higher valent metal ion. The water-soluble poly(meth)acrylamide (A) contains 2 mol % to 60 mol % of a constituent unit derived from a (meth)acrylamide group-containing compound (a), and 10 mol % to 50 mol % of a constituent unit derived from one or more unsaturated acids selected from the group consisting of unsaturated carboxylic acids and unsaturated sulfonic acids or an inorganic salt thereof (b). The divalent or higher valent metal ion is contained in an amount of 0.5 mol % to 30 mol % with respect to 100 mol % of an acid group contained in the component (b).

Thermally crosslinkable binder aqueous solution for lithium-ion battery, thermally crosslinkable slurry for lithium-ion battery negative electrode, negative electrode for lithium-ion battery

Provided are a thermally crosslinkable binder aqueous solution for a lithium-ion battery, a thermally crosslinkable slurry for a lithium-ion battery negative electrode, a negative electrode for a lithium-ion battery, a lithium-ion battery negative electrode material, as well as a lithium-ion battery and a method for producing the same. The present disclosure provides a thermally crosslinkable binder aqueous solution for a lithium-ion battery, containing water-soluble poly(meth)acrylamide (A) and having a pH of 5 to 7, wherein the water-soluble poly(meth)acrylamide (A) is a polymer of a monomer group containing, with respect to 100 mol % of the monomer group, 2 mol % to 60 mol % of a (meth)acrylamide group-containing compound (a), 10 mol % to 50 mol % of one or more unsaturated acids selected from the group consisting of unsaturated carboxylic acids and unsaturated sulfonic acids or an inorganic salt thereof (b), and 15 mol % to 78 mol % of hydroxyalkyl(meth)acrylate (c) having a hydroxyalkyl group having 2 to 4 carbon atoms.

Thermally crosslinkable binder aqueous solution for lithium-ion battery, thermally crosslinkable slurry for lithium-ion battery negative electrode, negative electrode for lithium-ion battery, lithium-ion battery negative electrode material, and lithium-ion battery and method for producing the same

A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

Processor apparatus and multithread processor apparatus

Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

Multithreaded processor

The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

Processing apparatus

A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n&#x3e;1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n&#x2212;1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.

Scan test control method and scan test circuit

A stored data modifier modifies data starting at any arbitrary address on a storage medium that should output a data word with a multi-byte width. A masked ROM outputs a 2-byte data word starting at an address specified as a multiple of 2by an address signal. A correspondence detector determines whether or not correspondence is found between a correction address and one of a number 2of addresses starting at, or preceding, the address specified by the address signal. If the correspondence detector has found the correspondence, a stored data selecting section selectively outputs, on a byte-by-byte basis, either the output of the masked ROM or correction data in accordance with the address signal and the correction address.

Circuit for modifying stored data

A processor that accesses a plurality of regions allocated to memory includes: a judging unit for judging which region is accessed based on an access address; an assuming unit for assuming which region is accessed based on the access address, the assuming unit producing an assumption result faster than the judging unit produces a judgement result; an accessing unit for starting access based on the assumption result; a detecting unit for detecting a disagreement between the judgement result and the assumption result; and a control unit for stopping the access that has been started if the detecting unit has detected the disagreement, and controlling the accessing unit to perform another access based on the judgement result.

Process containing address decoders suited to improvements in clock speed

A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.

Pipeline processor capable of reducing branch hazards with small-scale circuit

A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

Apparatus for pipelining sequential instructions in synchronism with an

A CPU (central processing unit) including an instruction processor and a data processor is connected with a ROM (read only memory) bus, a RAM (random access memory) bus, and an IO (input-output) bus for inputting/outputting data independently of the ROM and RAM buses. A rewritable register included in a memory access controller stores a set value of the number of wait cycles in an access to a ROM, a set value of the number of wait cycles in an access to a RAM, and a set value for switching an input path in the data processor. These set values can be varied according to a cycle time of a CPU clock signal. In accordance with these set values, insertion of wait cycles in the instruction processor and the data processor is controlled, and it is determined whether or not an input of the data processor is latched.

Central processing unit having a register which store values to vary

An instruction address that is referred to by a microprocessor unit is inputted over an instruction address bus and is stored. While counting the number of times a clock is fed to the microprocessor unit, a comparison is made between the stored instruction address and an instruction address that the microprocessor provides onto the instruction address bus. A clock count value, obtained at the time when the aforesaid instruction addresses agree, is stored. If a stored instruction address and an instruction address on the instruction address bus agree for every stored clock count value, then the microprocessor is judged to repeatedly execute a sequence of instructions and the loop count value is incremented by one. When the loop count value exceeds a predetermined value, the microprocessor is judged to be placed in an idle state and the clock frequency is lowered.

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Osaka, Japan

Shinji Ozaki