Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Shinji Nakazato

Hideaki Uchida

Nobuo Tanba

Kiyoo Itoh

Takao Watanabe

Yutaka Kobayashi

Ryoichi Hori

Goro Kitsukawa

Katsuhiro Shimohigashi

Takahide Ikeda

Noriyuki Homma

Masahiro Yamamura

Yoshikazu Saito

Takashi Akioka

Kinya Mitsumoto

Masanori Odaka

Yoshiaki Yazawa

Masao Shinozaki

Shusaku Miyata

Kenji Nishimoto

Yutaka Kohara

Sanae Asari

Atsushi Hiraishi

Kazunori Onozawa

Nobuyuki Gotoo

Nobuaki Miyakawa

Akihiko Emori

Noboru Akiyama

Sadayuki Ohkuma

Shuichi Miyaoka

Seigoh Yukutake

Yoshikasu Saito

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Semiconductor integrated circuit device

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.

Semiconductor device

Semiconductor memory device having separately biased wells for isolation

Semiconductor CMOS memory device with separately biased wells

Semiconductor memory device having bipolar transistor and structure to

A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

Memory device with improved common data line bias arrangement

A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

Growing community of inventors

Maebashi, Japan

Shinji Nakazato