Kabushiki Kaisha Toshiba

Shinji Nakatsuka

Shigeo Imai

Daisuke Kurose

Kazuhiro Oda

Shinsuke Fujii

Yosuke Ogawa

Sinnyoung Kim

An impedance measuring circuit has an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal, a peak hold circuit to hold a peak value of the output signal and to output a hold value, and an impedance calculation circuit to calculate the impedance in the target based on the hold value.

Impedance measuring circuit

According to an embodiment, a transmission circuit is configured to transmit a signal to a reception circuit through a transmitting AC coupling element. The transmitting AC coupling element is AC coupled to a receiving AC coupling element. The transmission circuit includes a drive signal generation circuit and a drive circuit. The drive signal generation circuit is configured to generate a drive signal in synchronization with a transmission signal to be transmitted. The drive circuit is configured to cause, in response to the drive signal, a drive current to flow between both ends of the transmitting AC coupling element in synchronization with a rising edge and a falling edge of the transmission signal during a driving period set in advance. The drive circuit is configured to apply an applied voltage to both of the ends of the transmitting AC coupling element after the driving period.

AC coupled transmission circuit and system

A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.

Semiconductor integrated circuit device

According to one embodiment, an amplification circuit includes first and second differential amplification circuits, each having an output connected to an output terminal and a feedback resistor connected between the output and a negative input of the respective differential amplification circuit. The amplification circuit includes a switching circuit that receives a first signal on first input terminal and a second signal on a second input terminal and includes set of switches that is configured to apply the first and second signals to the first and second differential amplification circuits such that in a first switching state an amplified voltage difference of the first and second signals is available between the two output terminals, and in a second switching state an amplified current difference of the first and second signals is available between the two output terminals.

Amplification circuit, amplification device, AFE circuit, and signal processing system

An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.

Growing community of inventors

Kamakura Kanagawa, Japan

Shinji Nakatsuka