Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Shinji Miyano

Tomoaki Yabe

Yoshihiro Ueda

Katsuhiko Sato

Tsuyoshi Kondo

Michael Arnaud Quinsat

Hideaki Aochi

Susumu Hashimoto

Yasuaki Ootera

Shiho Nakamura

Yasuhito Yoshimizu

Takuya Shimada

Tomoya Sanuki

Masaki Kado

Kenji Numata

Nobuyuki Umetsu

Yuichi Ito

Ryo Haga

Toshimasa Namekawa

Takeshi Nagai

Tohru Furuyama

Atsushi Suzuki

Osamu Wada

Atsushi Kawasumi

Ryo Fukuda

Masaharu Wada

Tsutomu Sato

Ichiro Mizushima

Tsuneo Inaba

Shinichi Yasuda

Takao Marukame

Takashi Yamada

Jun Deguchi

Hajime Nagano

Yoshifumi Nishi

Hidehiro Shiga

Daisuke Miyashita

Hironori Banba

Mutsumi Okajima

Hisato Oyamatsu

Mari Matsumoto

Hitoshi Iwai

Osamu Fujii

Yoshihiro Minami

Keniti Imamiya

Shinichi Nitta

Shuso Fujii

Takayuki Iwai

Shinichi Sasaki

A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Semiconductor storage device

A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.

Magnetic storage device

A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

Semiconductor memory device

According to one embodiment, there is provided a magnetic memory including a magnetic material column, a shift control circuit, and a write control circuit. The shift control circuit is connected to the magnetic material column. The write control circuit is configured to cause a current to flow through a write line passing near one end of the magnetic material column if writing data having a first value into the magnetic material column, and cause no current to flow through the write line if writing data having a second value into the magnetic material column.

Magnetic memory

According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.

Magnetic memory device

According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.

According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.

According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.

According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.

Magnetic memory device including magnetic portions nonmagnetic layers

According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.

According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.

According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

Arithmetic device

A semiconductor memory device includes a first and a second TFET whose gates and drains are cross-coupled. The drain of the first TFET is connected to a first node. The drain of the second TFET is connected to a second node. Included are a first access transistor connecting the first node to a first write bit line, a second access transistor connecting the second node to a second write bit line, and a third access transistor connecting the first node to a first read bit line. The first access transistor is constructed of a TFET connected in such a manner as that current flows from the first node to the first write bit line upon turning-on. The second access transistor is constructed of a TFET connected in such a manner as that current flows from the second node to the second write bit line upon turning-on.

Semiconductor memory device and method for driving the same

According to one embodiment, a semiconductor storage device includes a flip-flop circuit configured with two stages of inverters composed of TFETs. The flip-flop circuit includes first and second nodes. A first access transistor composed of a TFET is provided between the first node and a first write word-line. A second access transistor composed of a TFET is provided between the second node and a second write word-line. A MOS transistor which has a gate connected to the first node and responds to a voltage impressed on a read word-line to supply a voltage corresponding to a potential at the first node to a read bit-line is included. The first and second access transistors are configured with TFETs connected in a manner that a drain current flows from the first and second nodes to a write bit-line when turned on.

Semiconductor storage device having TFET access transistors and method of driving the same

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Yokohama Kanagawa, Japan

Shinji Miyano