International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Anest Iwata Corporation

Shinji Matsushima

Seiichi Kawano

Mitsuhiro Yamazaki

Takashi Inui

Masayoshi Nakano

Kenji Oka

Yasumichi Tsukamoto

Arimasa Naitoh

Takayuki Katoh

Hideshi Tsukamoto

Masahiko Nomura

Yuichi Shiraishi

Reiko Ohtani

Mitsuo Tabo

Sohichi Yokota

Saiichi Kawano

The present invention protects a memory image of an OS in a sleep state. A CPU executes a first OS or a second OS while switching there between. The first OS is loaded into a main memory, and the second OS is loaded into an auxiliary memory. The auxiliary memory may be connected to a chipset through a PCIe interface. The main memory and the auxiliary memory are configured such that, when one is in an active state where the right of access to the CPU is obtained, the other makes a transition to the sleep state where there is no right of access to the CPU while maintaining the memory image. In order to prevent one OS in the active state from accessing the main memory or the auxiliary memory in which the memory image of the other OS in the sleep state is stored, the BIOS may set a corresponding controller to disabled during a POST.

Arrangement for secure independent operating environments in a computer

Power usage of computing device components is controlled in a holistic manner. The projected total power consumption for the computing device to satisfy a power consumption policy for the device is determined. Power usage of each component of the computing device is controlled in a holistic manner&#x2014;i.e., balancing the power usage of the component against the power usage of other components&#x2014;so that the total power usage of the computing device falls within the projected total power consumption needed to satisfy the power consumption policy. How the user is currently utilizing the computing device may be periodically detected, based at least on a power consumption distribution of the components of the computing device. A current usage model is determined based on how the user is currently utilizing the computing device. The power usage of each component of the computing device is controlled based on the current usage model.

Controlling power usage of computing device components in holistic manner

A power supply circuit for a computer system includes an AC adapter designed to be connectable to the computer system and supplying power to the system, a main battery and a second battery that are designed to be connectable to the computer system and get charged with power from the AC adapter and then discharge it to supply power to the system, a charger that is a charging circuit for the main battery and/or the second battery while the main battery and/or the second battery is connected to the AC adapter with the computer system powered off, and a gate array circuit for turning off the power supply to an embedded controller.

Circuit for turning off charging function to a battery of a system based on information set by user during the system in power-off state

A computer apparatus provides control for automatically switching the apparatus between various operating modes requiring varying levels of power consumption. An embedded controller determines whether or not the computer apparatus is in motion (vibration, acceleration, rotation, etc.) on the basis of acceleration information obtained through an accelerometer provided in the computer apparatus. If the computer apparatus is in motion, the embedded controller provides control so as to prevent switching between system operating modes in order to protect certain components of the apparatus from damage which might be caused by switching operating modes while in motion.

Method and apparatus for preventing the transitioning of computer system power modes while the system is in motion

A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

Processing system and memory module having frequency selective memory

A scroll fluid machine has a fixed scroll in a housing and an orbiting scroll rotatably mounted to a driving shaft. A fixed wrap of the fixed scroll is engaged with an orbiting wrap of the orbiting scroll. The orbiting scroll is revolved at a certain eccentricity by the driving shaft, so that a gas sucked through the circumference of the housing is compressed as it moves toward the center, and discharged through the center. A gas-guiding bore is formed near the center of the orbiting scroll, and a heat-releasing rod is inserted in the bore. One end of the heat-releasing rod is projected from the fixed scroll to release heat to atmosphere.

Scroll fluid machine

There is provided an information processor including a central processing unit that includes an instruction execution module and has a normal mode for operating the instruction execution module and an execution halt mode for halting the instruction execution module. The information processor comprises a voltage controlling module for causing the instruction execution module to execute a voltage reduction instruction for placing the central processing unit into a low-voltage operation mode in which the operating voltage of the central processing unit is lowered from the operating voltage in the normal mode when the central processing unit switches from the normal mode to the execution halt mode; and a mode controlling module for placing the central processing unit into a low-voltage halt mode in which the instruction execution module is halted under the operating voltage for the low-voltage operation mode when the voltage controlling module places the central processing unit into the low-voltage operation mode.

Information processor, program, storage medium, and control method

A data server system and a computer apparatus is provided that can process external accesses reliably during mobile use. A main PC set in the suspend or hibernation mode during mobile use is configured so as to read/write data only from/to an MRAM having no mechanically movable parts and capable of withstanding higher levels of vibration than a hard disk drive (HDD) in response to a predetermined operation from a hand-held terminal. A power supply controller keeps power supplied to the MRAM and stops the supply of power to the HDD having mechanically movable parts. Whether or not the main PC is moving is decided automatically by detecting if the main PC is connected to an AC power source, a LAN cable, and a telephone cable.

Apparatus having durable storage

The present invention provides an apparatus that automatically designates a peripheral device as either a master or slave in response to the peripheral device connections when power is turned on. The apparatus comprises first and second connectors coupled to a master/slave designation means which provides a control signal to designate a peripheral device as a master.

Automatic master/slave designation for computer peripherals

An information processing system that can reduce the operating frequency of a CPU, or halt the operation of the CPU, at an adequate timing, even when the system is engaged in exchanging data with another independent apparatus (e.g., another PC) via a communication port (a serial port or a parallel port), or when a communication application is being executed. The system has (a) a CPU that operates in a normal mode, in a power saving mode in which less power is consumed than is required in a normal mode, or in a stop mode in which operation is completely halted; (b) at least one peripheral device; (c) a bus employed for communication between the CPU and the peripheral device; (d) a communication port, physically connected to another independent apparatus, for performing data transfer; (e) a bus cycle detector monitoring a bus cycle on the bus; (f) a state detector determining an operational mode of the CPU in response to a detection by the bus cycle of access of the communication port; (g) a signal generator providing, when the state detector ascertains that the operational mode is to be the power saving mode, a control signal to the CPU to set the CPU to the power saving mode; and (h) a CPU operation halting signal completely halting an operation of the CPU when the state determination means ascertains that the operational mode is to be the stop mode.

Method and system for improved power management in information

An information processing system which has (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) a termination detector detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) a time counter measuring a predetermined period of time after the completion of the predetermined transaction; and (f) a power saving control causing the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

Information processing system

Disclosed is a computer system that includes a CPU that can be operated both in a normal mode and in a power saving mode. The system further includes at least one peripheral device and a bus for allowing communication between the CPU and the peripheral device. A bus cycle detector monitors a bus cycle on the bus and a condition determiner determines the operation mode for the CPU in a specific bus cycle that is detected by the bus cycle detector. A signal generator is used to provide to the CPU, a control signal for changing the CPU's operation mode in accordance with a determination result obtained by the condition determiner. The disclosed system can reduce the operating frequency of a CPU or halt the operation of the CPU in accordance with an appropriate timing even when asynchronous communication is performed with peripheral devices.

Growing community of inventors

Yokohama, Japan

Shinji Matsushima