Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sanyo Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Sharp Corporation

Shinji Komori

Kenji Shima

Hiroaki Terada

Hidehiro Takata

Toshiyuki Tamura

Katsuhiko Asada

Hajime Asano

Masahisa Shimizu

Souichi Miyata

Hiroaki Nishikawa

Satoshi Matsumoto

Hiroki Miura

Fumiyasu Asai

Tetsuo Yamasaki

Hirono Tsubota

Hisakazu Sato

Mitsuo Meichi

Takeshi Fukuhara

Masaki Fujita

Soichi Miyata

Toshiya Okamoto

Satoru Kotoh

Akihiro Takeda

Kazuo Kyuma

Kenichi Shimomura

Hiroshi Kage

Takeharu Oshima

Shinji Nakashima

Narumi Sakashita

Yoshie Inaoka

Yasuhiko Nitta

Makoto Iwata

Yoshihiro Seguchi

Koichi Munakata

Shin'ichi Yoshida

Niroaki Nishikawa

Katsuhito Yamaguchi

Junji Onishi

Akira Kondo

Katushiko Asada

An apparatus for inputting information includes an image input section which acquires the image information through an image sensor, a motion calculation section which calculates a distance of movement based on the image information, an information selection section which selects symbol information from a symbol table in operatively interlocked relation with the calculated distance of movement, and an information display section which displays the symbol table and the selected symbol information.

Apparatus for inputting information and computer product

Intercommunication of data between adjacent element processors (3) is performed through a memory unit (6) which is independently accessible to the respective element processors (3) without interfere with the operations of the other element processors (3). Thus, memory access and data transfer can be achieved without interfere with the operations of individual element processor (3). Furthermore, it becomes possible to solve differential equations by asynchronous communication system.

Information processing system and method of computation performed with

A fuzzy development-support device includes a data input unit, a fuzzy-inference execution unit and a result verification unit. As an example, the data input unit includes a display unit connected to a membership function generator and a grid pitch designation unit for designating a grid pitch on a grid sheet displayed on the display unit for creation of membership functions. The grid pitch designation unit allows variation of grid pitch on the grid sheet. Thus, an operator uses the grid pitch designation unit to achieve an effective input of membership functions by generating the grid sheet with a pitch adequate for a desired shape of membership function.

Fuzzy development-support device

A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

Microprocessor and data flow microprocessor having vector operation

A memory apparatus and a data processor using the same, wherein a shift circuit 12 which shifts a word select signal generated by an address decoder 11 by a predetermined number of words and gives it to a memory when a predetermined signal is given from the outside, is included, and the word select signal, which is a decoded address signal inputted from the outside, is given intact to the memory when the predetermined signal is not given to the shift circuit 12, and the word select signal is shifted and given to the memory when the predetermined signal is given to the shift circuit 12, so that the word different word addresses are accessed when the same address signal is given, thereby the word contiguous to the inputted address can be accessed with a simple configuration and a small amount of hardwares and by restraining increase of power consumption.

Memory apparatus including a shift circuit for shifting a word select

A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

Data-driven processor having an output unit for providing only operand

A data-driven type computer system including an input limiting section for monitoring a current number of packets existing in the circular pipeline of the system while being processed. The input limiting section is adapted to control packets from being inputted from the external unit when the current number of packets exceeds a specified threshold value which is greater than a minimum packet number existing in the circular pipeline and which allows the attainment of the highest possible throughput of the system. The input limiting section further includes a predictive control unit to preliminarily analyze a current data flow graph to be processed in the system and also to take order in rank a possible rate of increase in the quantity of packets generated by a copying operation as well as a possible rate of reduction in the prior processing by the system. While being stored once for buffering by an input buffer, variation in the current quantity of deposited packets is predicted by the predictive control unit every time when packets are entered from an external source or from the output section, so that they are prevented from being entered by the input limiting section when the current quantity of deposited packets is in excess of the preset limit of the hardware.

Data-flow processing system having an input packet limiting section for

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Data flow processor with data processing and next address determination

A data retrieving apparatus comprising an address an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgment of said associative memory unit.

Taken storage apparatus using a hash memory and a cam

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Associative storage for data packets including asynchronous,

An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.

Pipeline processor with self timed data transfer

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Data flow processor with next destination node determination

A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgement of said associative memory unit.

Retrieving data using hash memory address generated by reversing /xor

A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Parallel processing development system with debugging device includes

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Itami, Japan

Shinji Komori