Sharp Kabushiki Kaisha Corporation

Omron Corporation

Toppan Printing Co., Ltd.

Shinji Kobayashi

Tomohiro Okada

Akiro Kobayashi

Masashi Inoue

Kazuya Ishihara

Nobuyoshi Awaya

Yukio Tamai

Yasunari Hosoi

Hidetoshi Masuda

Toshimasa Suzuki

Hidechika Kawazoe

Eiji Aoki

Kunio Watanabe

Yuji Matsushita

Naoto Hagiwara

Yuji Nishi

Toshiyuki Marumo

Shinji Akima

Holder for a transportation robot

Transportation robot

Provided is a variable resistance element capable of performing a stable resistance switching operation and having a favorable resistance value retention characteristics, comprising a variable resistorsandwiched between a upper electrodeand lower electrodeand formed of titanium oxide or titanium oxynitride having a crystal grain diameter of 30 nm or less. When the variable resistanceis formed under the substrate temperature of 150&#xb0; C. to 500&#xb0; C., an anatase-type crystal having a crystal grain diameter of 30 nm or less is formed. Since the crystalline state of the variable resistor changes by applying a voltage pulse and the resistance value changes, no forming process is required. Moreover, it is possible to perform a stable resistance switching operation and obtain an excellent effect that the resistance fluctuation is small even if the switching is repeated, or the variable resistance element is stored for a long time under a high temperature.

Variable resistance element, its manufacturing method and semiconductor memory device comprising the same

A variable resistance element is configured to be provided with a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance between the first electrode and the second electrode is changed by applying a voltage pulse of a predetermined polarity between the first electrode and the second electrode, and the variable resistance element has a resistance hysteresis characteristic, in which a changing rate of a resistance value is changed from positive to negative with respect to increase of a cumulative pulse applying time in the application of the voltage pulse. The voltage pulse is applied to the variable resistance element so that the cumulative pulse applying time is not longer than a specific cumulative pulse applying time, in which the changing rate of the, resistance value is changed from positive to negative with respect to increase of the cumulative pulse applying time in the resistance hysteresis characteristic.

Driving method of variable resistance element and memory device

In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.

Nonvolatile semiconductor memory device comprising a variable resistive element containing a perovskite-type crystal structure

The present invention provides a photomask defect testing method, a photomask manufacturing method and a semiconductor integrated circuit manufacturing method. In the photomask defect testing method, reference data is created from corrected photomask design data that is corrected on the basis of an exposure transfer pattern, and sensor data is created by measuring the shape of the photomask based on the corrected photomask design data. Furthermore, first non-testing region data indicating non-testing regions including pattern portions having a predetermined width or less and pattern spaces having a predetermined value or less is extracted from the corrected photomask design data, the extracted first non-testing region data is stored so as to be included in the corrected photomask design data, the non-testing regions indicated by the first non-testing region data is excluded, and the reference data is compared with the sensor data, whereby defects on the photomask are detected.

Photomask defect testing method, photomask manufacturing method and semiconductor integrated circuit manufacturing method

A mask pattern for multiple exposure for forming a resist pattern with an unvarying pattern pitch on a semiconductor wafer, which is utilized as in case where a mask pattern under a design having the width of an aperture pattern smaller than the width of a light-shielding pattern is used at one exposure, wherein the mask pattern for multiple exposure has a pattern pitch that is the same as that of the mask pattern under design and has the width of an aperture pattern greater than the width of a light-shielding pattern.

Mask pattern and method for forming resist pattern using mask pattern thereof

A method for forming a resist pattern comprising the steps of: forming a light-shield film on an overall surface of a transparent substrate; forming a resist layer and an organic film being capable of functioning as a trap layer or an electron beam buffer layer against electrons on an overall surface of the light-shield film in this order; carrying out exposure in a desired pattern above the organic film; and developing the resist layer and the organic film to form a desired pattern in the resist layer.

Method for forming resist pattern

A method of producing a chromium mask, said method comprising forming a chromium film on a mask substrate, forming a resist layer on the chromium film, patterning the resist layer in desired shape, performing plasma treatment with a fluorine-containing gas on the resist pattern, and finally performing dry etching on the chromium film by using the resist pattern as a mask.

Method of producing chromium mask

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Nara, Japan

Shinji Kobayashi