Kabushiki Kaisha Toshiba

Shinji Kitabayashi

Yukihiro Urakawa

Kazutaka Nogami

Tatsuya Higashi

Junya Shirakura

Ryoko Usuba

The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.

Semiconductor integrated circuit wiring design method and semiconductor integrated circuit

The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity

In a circuit in which logic cells are regularly arranged, to supply to a substrate substrate potentials different from a power supply voltage and ground voltage which are supplied to sources of transistors in the cell, substrate potential supplying cells are arranged in a region in which the logic cells are arranged. The substrate potential supplying cells are connected to the substrate potentials through an n-type substrate potential NSUB line and p-type substrate potential PSUB line. The substrate potentials are supplied to apply them to the substrate. If the substrate potential lines are arranged in the logic cell region, the element area is greatly reduced. However, using the substrate potential supplying cells VSC can improve area efficiency.

Semiconductor integrated circuit

An adder comprises: a comparator circuit for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each other; a non-volatile memory having first to n&plus;1-th word lines, m (2 &gE;n&plus;1) bit lines which are provided so as to intersect the word lines, and memory cells, each of which is provided at an intersection of each of the word lines and each of the bit lines and each of which has stored 1-bit data; and a selector circuit for selecting one of the n&plus;1 word lines on the basis of n comparison results of the comparator circuit to activate the selected word line. Thus, a plurality of bits are added at high speed.

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Tokyo, Japan

Shinji Kitabayashi